Home
last modified time | relevance | path

Searched refs:TSFlags (Results 1 – 25 of 171) sorted by relevance

1234567

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h301 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
305 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
309 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
313 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
325 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
329 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
333 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
337 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
341 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
345 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
[all …]
DSIInstrFormats.td125 let TSFlags{0} = SALU;
126 let TSFlags{1} = VALU;
128 let TSFlags{2} = SOP1;
129 let TSFlags{3} = SOP2;
130 let TSFlags{4} = SOPC;
131 let TSFlags{5} = SOPK;
132 let TSFlags{6} = SOPP;
134 let TSFlags{7} = VOP1;
135 let TSFlags{8} = VOP2;
136 let TSFlags{9} = VOPC;
[all …]
DR600InstrFormats.td54 let TSFlags{4} = Trig;
55 let TSFlags{5} = Op3;
59 let TSFlags{6} = isVector;
60 let TSFlags{8-7} = FlagOperandIdx;
61 let TSFlags{9} = HasNativeOperands;
62 let TSFlags{10} = Op1;
63 let TSFlags{11} = Op2;
64 let TSFlags{12} = VTXInst;
65 let TSFlags{13} = TEXInst;
66 let TSFlags{14} = ALUInst;
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h184 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
188 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
192 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
196 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
208 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
212 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
216 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
220 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
224 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
228 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
[all …]
DSIInstrFormats.td54 let TSFlags{0} = VM_CNT;
55 let TSFlags{1} = EXP_CNT;
56 let TSFlags{2} = LGKM_CNT;
58 let TSFlags{3} = SALU;
59 let TSFlags{4} = VALU;
61 let TSFlags{5} = SOP1;
62 let TSFlags{6} = SOP2;
63 let TSFlags{7} = SOPC;
64 let TSFlags{8} = SOPK;
65 let TSFlags{9} = SOPP;
[all …]
DR600InstrFormats.td44 let TSFlags{4} = Trig;
45 let TSFlags{5} = Op3;
49 let TSFlags{6} = isVector;
50 let TSFlags{8-7} = FlagOperandIdx;
51 let TSFlags{9} = HasNativeOperands;
52 let TSFlags{10} = Op1;
53 let TSFlags{11} = Op2;
54 let TSFlags{12} = VTXInst;
55 let TSFlags{13} = TEXInst;
56 let TSFlags{14} = ALUInst;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonInstrFormats.td72 let TSFlags{5-0} = Type.Value;
76 let TSFlags{6} = isSolo;
79 let TSFlags{7} = isSoloAX;
82 let TSFlags{8} = isRestrictSlot1AOK;
86 let TSFlags{9} = isPredicated;
88 let TSFlags{10} = isPredicatedFalse;
90 let TSFlags{11} = isPredicatedNew;
92 let TSFlags{12} = isPredicateLate; // Late predicate producer insn.
96 let TSFlags{13} = isNewValue; // New-value consumer insn.
98 let TSFlags{14} = hasNewValue; // New-value producer insn.
[all …]
DHexagonInstrFormatsV4.td52 let TSFlags{5-0} = Type.Value;
56 let TSFlags{6} = isPredicated;
58 let TSFlags{7} = isPredicatedFalse;
60 let TSFlags{8} = isPredicatedNew;
64 let TSFlags{9} = isNewValue; // New-value consumer insn.
66 let TSFlags{10} = hasNewValue; // New-value producer insn.
68 let TSFlags{13-11} = opNewValue; // New-value produced operand.
70 let TSFlags{14} = isNVStorable; // Store that can become new-value store.
72 let TSFlags{15} = isNVStore; // New-value store insn.
76 let TSFlags{16} = isExtendable; // Insn may be extended.
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp115 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
121 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
125 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
129 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
151 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { in getImmFixupKind() argument
152 unsigned Size = X86II::getSizeOfImm(TSFlags); in getImmFixupKind()
153 bool isPCRel = X86II::isImmPCRel(TSFlags); in getImmFixupKind()
243 uint64_t TSFlags, unsigned &CurByte, in EmitMemModRMByte() argument
271 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0; in EmitMemModRMByte()
386 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, in EmitVEXOpcodePrefix() argument
[all …]
DX86BaseInfo.h417 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { in getBaseOpcodeFor() argument
418 return TSFlags >> X86II::OpcodeShift; in getBaseOpcodeFor()
421 static inline bool hasImm(uint64_t TSFlags) { in hasImm() argument
422 return (TSFlags & X86II::ImmMask) != 0; in hasImm()
427 static inline unsigned getSizeOfImm(uint64_t TSFlags) { in getSizeOfImm() argument
428 switch (TSFlags & X86II::ImmMask) { in getSizeOfImm()
442 static inline unsigned isImmPCRel(uint64_t TSFlags) { in isImmPCRel() argument
443 switch (TSFlags & X86II::ImmMask) { in isImmPCRel()
465 static inline int getMemoryOperandNo(uint64_t TSFlags) { in getMemoryOperandNo() argument
466 switch (TSFlags & X86II::FormMask) { in getMemoryOperandNo()
[all …]
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp126 uint64_t TSFlags, bool Rex, unsigned &CurByte,
134 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
141 bool emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
145 uint8_t DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
165 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) { in isCDisp8() argument
166 assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) && in isCDisp8()
170 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift; in isCDisp8()
190 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { in getImmFixupKind() argument
191 unsigned Size = X86II::getSizeOfImm(TSFlags); in getImmFixupKind()
192 bool isPCRel = X86II::isImmPCRel(TSFlags); in getImmFixupKind()
[all …]
DX86BaseInfo.h564 inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { in getBaseOpcodeFor() argument
565 return TSFlags >> X86II::OpcodeShift; in getBaseOpcodeFor()
568 inline bool hasImm(uint64_t TSFlags) { in hasImm() argument
569 return (TSFlags & X86II::ImmMask) != 0; in hasImm()
574 inline unsigned getSizeOfImm(uint64_t TSFlags) { in getSizeOfImm() argument
575 switch (TSFlags & X86II::ImmMask) { in getSizeOfImm()
590 inline unsigned isImmPCRel(uint64_t TSFlags) { in isImmPCRel() argument
591 switch (TSFlags & X86II::ImmMask) { in isImmPCRel()
608 inline unsigned isImmSigned(uint64_t TSFlags) { in isImmSigned() argument
609 switch (TSFlags & X86II::ImmMask) { in isImmSigned()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp134 uint64_t TSFlags, bool Rex, unsigned &CurByte,
142 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
149 bool emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
153 uint8_t DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
169 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) { in isCDisp8() argument
170 assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) && in isCDisp8()
174 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift; in isCDisp8()
194 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { in getImmFixupKind() argument
195 unsigned Size = X86II::getSizeOfImm(TSFlags); in getImmFixupKind()
196 bool isPCRel = X86II::isImmPCRel(TSFlags); in getImmFixupKind()
[all …]
DX86BaseInfo.h583 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) { in getBaseOpcodeFor() argument
584 return TSFlags >> X86II::OpcodeShift; in getBaseOpcodeFor()
587 inline bool hasImm(uint64_t TSFlags) { in hasImm() argument
588 return (TSFlags & X86II::ImmMask) != 0; in hasImm()
593 inline unsigned getSizeOfImm(uint64_t TSFlags) { in getSizeOfImm() argument
594 switch (TSFlags & X86II::ImmMask) { in getSizeOfImm()
610 inline unsigned isImmPCRel(uint64_t TSFlags) { in isImmPCRel() argument
611 switch (TSFlags & X86II::ImmMask) { in isImmPCRel()
629 inline unsigned isImmSigned(uint64_t TSFlags) { in isImmSigned() argument
630 switch (TSFlags & X86II::ImmMask) { in isImmSigned()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/
DNVPTXInstrFormats.td50 let TSFlags{3-0} = VecInstType;
51 let TSFlags{4-4} = IsSimpleMove;
52 let TSFlags{5-5} = IsLoad;
53 let TSFlags{6-6} = IsStore;
54 let TSFlags{7} = IsTex;
55 let TSFlags{9-8} = IsSuld;
56 let TSFlags{10} = IsSust;
57 let TSFlags{11} = IsSurfTexQuery;
58 let TSFlags{12} = IsTexModeUnified;
DNVPTXReplaceImageHandles.cpp83 if (MCID.TSFlags & NVPTXII::IsTexFlag) { in processInstr()
89 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) { in processInstr()
95 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) { in processInstr()
97 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1); in processInstr()
105 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) { in processInstr()
112 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) { in processInstr()
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrFormats.td50 let TSFlags{3-0} = VecInstType;
51 let TSFlags{4-4} = IsSimpleMove;
52 let TSFlags{5-5} = IsLoad;
53 let TSFlags{6-6} = IsStore;
54 let TSFlags{7} = IsTex;
55 let TSFlags{9-8} = IsSuld;
56 let TSFlags{10} = IsSust;
57 let TSFlags{11} = IsSurfTexQuery;
58 let TSFlags{12} = IsTexModeUnified;
DNVPTXInstrInfo.cpp73 unsigned TSFlags = in isMoveInstr() local
74 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift; in isMoveInstr()
75 isMove = (TSFlags == 1); in isMoveInstr()
94 unsigned TSFlags = in isLoadInstr() local
95 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift; in isLoadInstr()
96 isLoad = (TSFlags == 1); in isLoadInstr()
105 unsigned TSFlags = in isStoreInstr() local
106 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift; in isStoreInstr()
107 isStore = (TSFlags == 1); in isStoreInstr()
DNVPTXReplaceImageHandles.cpp83 if (MCID.TSFlags & NVPTXII::IsTexFlag) { in processInstr()
89 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) { in processInstr()
95 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) { in processInstr()
97 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1); in processInstr()
105 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) { in processInstr()
112 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) { in processInstr()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrFormatsV4.td64 let TSFlags{4-0} = Type.Value;
68 let TSFlags{6} = isPredicated;
70 let TSFlags{7} = isPredicatedFalse;
72 let TSFlags{8} = isPredicatedNew;
76 let TSFlags{9} = isNewValue; // New-value consumer insn.
78 let TSFlags{10} = hasNewValue; // New-value producer insn.
80 let TSFlags{13-11} = opNewValue; // New-value produced operand.
82 let TSFlags{14} = isNVStorable; // Store that can become new-value store.
84 let TSFlags{15} = isNVStore; // New-value store insn.
88 let TSFlags{16} = isExtendable; // Insn may be extended.
[all …]
DHexagonInstrFormats.td102 let TSFlags{4-0} = Type.Value;
106 let TSFlags{5} = isSolo;
109 let TSFlags{6} = isSoloAX;
112 let TSFlags{7} = isSoloAin1;
116 let TSFlags{8} = isPredicated;
118 let TSFlags{9} = isPredicatedFalse;
120 let TSFlags{10} = isPredicatedNew;
122 let TSFlags{11} = isPredicateLate; // Late predicate producer insn.
126 let TSFlags{12} = isNewValue; // New-value consumer insn.
128 let TSFlags{13} = hasNewValue; // New-value producer insn.
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInstrInfo.cpp213 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
220 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
288 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
306 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
312 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
318 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
351 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
376 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp2()
395 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags; in getType()
465 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in hasNewValue()
[all …]
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInstrInfo.cpp170 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAccessSize()
178 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getBitCount()
185 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getCExtOpNum()
251 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
269 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
275 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
283 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMaxValue()
298 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMinValue()
316 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
322 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOperand()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86CodeEmitter.cpp154 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) in determineREX()
156 if (Desc.TSFlags & X86II::REX_W) in determineREX()
175 switch (Desc.TSFlags & X86II::FormMask) { in determineREX()
631 if (Desc->TSFlags & X86II::LOCK) in emitInstruction()
635 switch (Desc->TSFlags & X86II::SegOvrMask) { in emitInstruction()
647 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) in emitInstruction()
651 if (Desc->TSFlags & X86II::OpSize) in emitInstruction()
655 if (Desc->TSFlags & X86II::AdSize) in emitInstruction()
659 switch (Desc->TSFlags & X86II::Op0Mask) { in emitInstruction()
683 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8) in emitInstruction()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrFMA3Info.cpp133 const X86InstrFMA3Group *llvm::getFMA3Group(unsigned Opcode, uint64_t TSFlags) { in getFMA3Group() argument
136 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group()
137 bool IsFMA3 = ((TSFlags & X86II::EncodingMask) == X86II::VEX || in getFMA3Group()
138 (TSFlags & X86II::EncodingMask) == X86II::EVEX) && in getFMA3Group()
139 (TSFlags & X86II::OpMapMask) == X86II::T8 && in getFMA3Group()
140 (TSFlags & X86II::OpPrefixMask) == X86II::PD && in getFMA3Group()
150 if (TSFlags & X86II::EVEX_RC) in getFMA3Group()
152 else if (TSFlags & X86II::EVEX_B) in getFMA3Group()

1234567