1//===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// R600 Instruction format definitions. 11// 12//===----------------------------------------------------------------------===// 13 14def isR600 : Predicate<"Subtarget->getGeneration() <= AMDGPUSubtarget::R700">; 15 16def isR600toCayman : Predicate< 17 "Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">; 18 19class R600Pat<dag pattern, dag result> : AMDGPUPat<pattern, result> { 20 let SubtargetPredicate = isR600toCayman; 21} 22 23class InstR600 <dag outs, dag ins, string asm, list<dag> pattern, 24 InstrItinClass itin = NoItinerary> 25 : AMDGPUInst <outs, ins, asm, pattern>, PredicateControl { 26 27 field bits<64> Inst; 28 bit Trig = 0; 29 bit Op3 = 0; 30 bit isVector = 0; 31 bits<2> FlagOperandIdx = 0; 32 bit Op1 = 0; 33 bit Op2 = 0; 34 bit LDS_1A = 0; 35 bit LDS_1A1D = 0; 36 bit HasNativeOperands = 0; 37 bit VTXInst = 0; 38 bit TEXInst = 0; 39 bit ALUInst = 0; 40 bit IsExport = 0; 41 bit LDS_1A2D = 0; 42 43 let SubtargetPredicate = isR600toCayman; 44 let Namespace = "R600"; 45 let OutOperandList = outs; 46 let InOperandList = ins; 47 let AsmString = asm; 48 let Pattern = pattern; 49 let Itinerary = itin; 50 51 // No AsmMatcher support. 52 let isCodeGenOnly = 1; 53 54 let TSFlags{4} = Trig; 55 let TSFlags{5} = Op3; 56 57 // Vector instructions are instructions that must fill all slots in an 58 // instruction group 59 let TSFlags{6} = isVector; 60 let TSFlags{8-7} = FlagOperandIdx; 61 let TSFlags{9} = HasNativeOperands; 62 let TSFlags{10} = Op1; 63 let TSFlags{11} = Op2; 64 let TSFlags{12} = VTXInst; 65 let TSFlags{13} = TEXInst; 66 let TSFlags{14} = ALUInst; 67 let TSFlags{15} = LDS_1A; 68 let TSFlags{16} = LDS_1A1D; 69 let TSFlags{17} = IsExport; 70 let TSFlags{18} = LDS_1A2D; 71} 72 73//===----------------------------------------------------------------------===// 74// ALU instructions 75//===----------------------------------------------------------------------===// 76 77class R600_ALU_LDS_Word0 { 78 field bits<32> Word0; 79 80 bits<11> src0; 81 bits<1> src0_rel; 82 bits<11> src1; 83 bits<1> src1_rel; 84 bits<3> index_mode = 0; 85 bits<2> pred_sel; 86 bits<1> last; 87 88 bits<9> src0_sel = src0{8-0}; 89 bits<2> src0_chan = src0{10-9}; 90 bits<9> src1_sel = src1{8-0}; 91 bits<2> src1_chan = src1{10-9}; 92 93 let Word0{8-0} = src0_sel; 94 let Word0{9} = src0_rel; 95 let Word0{11-10} = src0_chan; 96 let Word0{21-13} = src1_sel; 97 let Word0{22} = src1_rel; 98 let Word0{24-23} = src1_chan; 99 let Word0{28-26} = index_mode; 100 let Word0{30-29} = pred_sel; 101 let Word0{31} = last; 102} 103 104class R600ALU_Word0 : R600_ALU_LDS_Word0 { 105 106 bits<1> src0_neg; 107 bits<1> src1_neg; 108 109 let Word0{12} = src0_neg; 110 let Word0{25} = src1_neg; 111} 112 113class R600ALU_Word1 { 114 field bits<32> Word1; 115 116 bits<11> dst; 117 bits<3> bank_swizzle; 118 bits<1> dst_rel; 119 bits<1> clamp; 120 121 bits<7> dst_sel = dst{6-0}; 122 bits<2> dst_chan = dst{10-9}; 123 124 let Word1{20-18} = bank_swizzle; 125 let Word1{27-21} = dst_sel; 126 let Word1{28} = dst_rel; 127 let Word1{30-29} = dst_chan; 128 let Word1{31} = clamp; 129} 130 131class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{ 132 133 bits<1> src0_abs; 134 bits<1> src1_abs; 135 bits<1> update_exec_mask; 136 bits<1> update_pred; 137 bits<1> write; 138 bits<2> omod; 139 140 let Word1{0} = src0_abs; 141 let Word1{1} = src1_abs; 142 let Word1{2} = update_exec_mask; 143 let Word1{3} = update_pred; 144 let Word1{4} = write; 145 let Word1{6-5} = omod; 146 let Word1{17-7} = alu_inst; 147} 148 149class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{ 150 151 bits<11> src2; 152 bits<1> src2_rel; 153 bits<1> src2_neg; 154 155 bits<9> src2_sel = src2{8-0}; 156 bits<2> src2_chan = src2{10-9}; 157 158 let Word1{8-0} = src2_sel; 159 let Word1{9} = src2_rel; 160 let Word1{11-10} = src2_chan; 161 let Word1{12} = src2_neg; 162 let Word1{17-13} = alu_inst; 163} 164 165class R600LDS_Word1 { 166 field bits<32> Word1; 167 168 bits<11> src2; 169 bits<9> src2_sel = src2{8-0}; 170 bits<2> src2_chan = src2{10-9}; 171 bits<1> src2_rel; 172 // offset specifies the stride offset to the second set of data to be read 173 // from. This is a dword offset. 174 bits<5> alu_inst = 17; // OP3_INST_LDS_IDX_OP 175 bits<3> bank_swizzle; 176 bits<6> lds_op; 177 bits<2> dst_chan = 0; 178 179 let Word1{8-0} = src2_sel; 180 let Word1{9} = src2_rel; 181 let Word1{11-10} = src2_chan; 182 let Word1{17-13} = alu_inst; 183 let Word1{20-18} = bank_swizzle; 184 let Word1{26-21} = lds_op; 185 let Word1{30-29} = dst_chan; 186} 187 188 189/* 190XXX: R600 subtarget uses a slightly different encoding than the other 191subtargets. We currently handle this in R600MCCodeEmitter, but we may 192want to use these instruction classes in the future. 193 194class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 { 195 196 bits<1> fog_merge; 197 bits<10> alu_inst; 198 199 let Inst{37} = fog_merge; 200 let Inst{39-38} = omod; 201 let Inst{49-40} = alu_inst; 202} 203 204class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 { 205 206 bits<11> alu_inst; 207 208 let Inst{38-37} = omod; 209 let Inst{49-39} = alu_inst; 210} 211*/ 212 213//===----------------------------------------------------------------------===// 214// Vertex Fetch instructions 215//===----------------------------------------------------------------------===// 216 217class VTX_WORD0 { 218 field bits<32> Word0; 219 bits<7> src_gpr; 220 bits<5> VC_INST; 221 bits<2> FETCH_TYPE; 222 bits<1> FETCH_WHOLE_QUAD; 223 bits<8> buffer_id; 224 bits<1> SRC_REL; 225 bits<2> SRC_SEL_X; 226 227 let Word0{4-0} = VC_INST; 228 let Word0{6-5} = FETCH_TYPE; 229 let Word0{7} = FETCH_WHOLE_QUAD; 230 let Word0{15-8} = buffer_id; 231 let Word0{22-16} = src_gpr; 232 let Word0{23} = SRC_REL; 233 let Word0{25-24} = SRC_SEL_X; 234} 235 236class VTX_WORD0_eg : VTX_WORD0 { 237 238 bits<6> MEGA_FETCH_COUNT; 239 240 let Word0{31-26} = MEGA_FETCH_COUNT; 241} 242 243class VTX_WORD0_cm : VTX_WORD0 { 244 245 bits<2> SRC_SEL_Y; 246 bits<2> STRUCTURED_READ; 247 bits<1> LDS_REQ; 248 bits<1> COALESCED_READ; 249 250 let Word0{27-26} = SRC_SEL_Y; 251 let Word0{29-28} = STRUCTURED_READ; 252 let Word0{30} = LDS_REQ; 253 let Word0{31} = COALESCED_READ; 254} 255 256class VTX_WORD1_GPR { 257 field bits<32> Word1; 258 bits<7> dst_gpr; 259 bits<1> DST_REL; 260 bits<3> DST_SEL_X; 261 bits<3> DST_SEL_Y; 262 bits<3> DST_SEL_Z; 263 bits<3> DST_SEL_W; 264 bits<1> USE_CONST_FIELDS; 265 bits<6> DATA_FORMAT; 266 bits<2> NUM_FORMAT_ALL; 267 bits<1> FORMAT_COMP_ALL; 268 bits<1> SRF_MODE_ALL; 269 270 let Word1{6-0} = dst_gpr; 271 let Word1{7} = DST_REL; 272 let Word1{8} = 0; // Reserved 273 let Word1{11-9} = DST_SEL_X; 274 let Word1{14-12} = DST_SEL_Y; 275 let Word1{17-15} = DST_SEL_Z; 276 let Word1{20-18} = DST_SEL_W; 277 let Word1{21} = USE_CONST_FIELDS; 278 let Word1{27-22} = DATA_FORMAT; 279 let Word1{29-28} = NUM_FORMAT_ALL; 280 let Word1{30} = FORMAT_COMP_ALL; 281 let Word1{31} = SRF_MODE_ALL; 282} 283 284//===----------------------------------------------------------------------===// 285// Texture fetch instructions 286//===----------------------------------------------------------------------===// 287 288class TEX_WORD0 { 289 field bits<32> Word0; 290 291 bits<5> TEX_INST; 292 bits<2> INST_MOD; 293 bits<1> FETCH_WHOLE_QUAD; 294 bits<8> RESOURCE_ID; 295 bits<7> SRC_GPR; 296 bits<1> SRC_REL; 297 bits<1> ALT_CONST; 298 bits<2> RESOURCE_INDEX_MODE; 299 bits<2> SAMPLER_INDEX_MODE; 300 301 let Word0{4-0} = TEX_INST; 302 let Word0{6-5} = INST_MOD; 303 let Word0{7} = FETCH_WHOLE_QUAD; 304 let Word0{15-8} = RESOURCE_ID; 305 let Word0{22-16} = SRC_GPR; 306 let Word0{23} = SRC_REL; 307 let Word0{24} = ALT_CONST; 308 let Word0{26-25} = RESOURCE_INDEX_MODE; 309 let Word0{28-27} = SAMPLER_INDEX_MODE; 310} 311 312class TEX_WORD1 { 313 field bits<32> Word1; 314 315 bits<7> DST_GPR; 316 bits<1> DST_REL; 317 bits<3> DST_SEL_X; 318 bits<3> DST_SEL_Y; 319 bits<3> DST_SEL_Z; 320 bits<3> DST_SEL_W; 321 bits<7> LOD_BIAS; 322 bits<1> COORD_TYPE_X; 323 bits<1> COORD_TYPE_Y; 324 bits<1> COORD_TYPE_Z; 325 bits<1> COORD_TYPE_W; 326 327 let Word1{6-0} = DST_GPR; 328 let Word1{7} = DST_REL; 329 let Word1{11-9} = DST_SEL_X; 330 let Word1{14-12} = DST_SEL_Y; 331 let Word1{17-15} = DST_SEL_Z; 332 let Word1{20-18} = DST_SEL_W; 333 let Word1{27-21} = LOD_BIAS; 334 let Word1{28} = COORD_TYPE_X; 335 let Word1{29} = COORD_TYPE_Y; 336 let Word1{30} = COORD_TYPE_Z; 337 let Word1{31} = COORD_TYPE_W; 338} 339 340class TEX_WORD2 { 341 field bits<32> Word2; 342 343 bits<5> OFFSET_X; 344 bits<5> OFFSET_Y; 345 bits<5> OFFSET_Z; 346 bits<5> SAMPLER_ID; 347 bits<3> SRC_SEL_X; 348 bits<3> SRC_SEL_Y; 349 bits<3> SRC_SEL_Z; 350 bits<3> SRC_SEL_W; 351 352 let Word2{4-0} = OFFSET_X; 353 let Word2{9-5} = OFFSET_Y; 354 let Word2{14-10} = OFFSET_Z; 355 let Word2{19-15} = SAMPLER_ID; 356 let Word2{22-20} = SRC_SEL_X; 357 let Word2{25-23} = SRC_SEL_Y; 358 let Word2{28-26} = SRC_SEL_Z; 359 let Word2{31-29} = SRC_SEL_W; 360} 361 362//===----------------------------------------------------------------------===// 363// Control Flow Instructions 364//===----------------------------------------------------------------------===// 365 366class CF_WORD1_R600 { 367 field bits<32> Word1; 368 369 bits<3> POP_COUNT; 370 bits<5> CF_CONST; 371 bits<2> COND; 372 bits<3> COUNT; 373 bits<6> CALL_COUNT; 374 bits<1> COUNT_3; 375 bits<1> END_OF_PROGRAM; 376 bits<1> VALID_PIXEL_MODE; 377 bits<7> CF_INST; 378 bits<1> WHOLE_QUAD_MODE; 379 bits<1> BARRIER; 380 381 let Word1{2-0} = POP_COUNT; 382 let Word1{7-3} = CF_CONST; 383 let Word1{9-8} = COND; 384 let Word1{12-10} = COUNT; 385 let Word1{18-13} = CALL_COUNT; 386 let Word1{19} = COUNT_3; 387 let Word1{21} = END_OF_PROGRAM; 388 let Word1{22} = VALID_PIXEL_MODE; 389 let Word1{29-23} = CF_INST; 390 let Word1{30} = WHOLE_QUAD_MODE; 391 let Word1{31} = BARRIER; 392} 393 394class CF_WORD0_EG { 395 field bits<32> Word0; 396 397 bits<24> ADDR; 398 bits<3> JUMPTABLE_SEL; 399 400 let Word0{23-0} = ADDR; 401 let Word0{26-24} = JUMPTABLE_SEL; 402} 403 404class CF_WORD1_EG { 405 field bits<32> Word1; 406 407 bits<3> POP_COUNT; 408 bits<5> CF_CONST; 409 bits<2> COND; 410 bits<6> COUNT; 411 bits<1> VALID_PIXEL_MODE; 412 bits<1> END_OF_PROGRAM; 413 bits<8> CF_INST; 414 bits<1> BARRIER; 415 416 let Word1{2-0} = POP_COUNT; 417 let Word1{7-3} = CF_CONST; 418 let Word1{9-8} = COND; 419 let Word1{15-10} = COUNT; 420 let Word1{20} = VALID_PIXEL_MODE; 421 let Word1{21} = END_OF_PROGRAM; 422 let Word1{29-22} = CF_INST; 423 let Word1{31} = BARRIER; 424} 425 426class CF_ALU_WORD0 { 427 field bits<32> Word0; 428 429 bits<22> ADDR; 430 bits<4> KCACHE_BANK0; 431 bits<4> KCACHE_BANK1; 432 bits<2> KCACHE_MODE0; 433 434 let Word0{21-0} = ADDR; 435 let Word0{25-22} = KCACHE_BANK0; 436 let Word0{29-26} = KCACHE_BANK1; 437 let Word0{31-30} = KCACHE_MODE0; 438} 439 440class CF_ALU_WORD1 { 441 field bits<32> Word1; 442 443 bits<2> KCACHE_MODE1; 444 bits<8> KCACHE_ADDR0; 445 bits<8> KCACHE_ADDR1; 446 bits<7> COUNT; 447 bits<1> ALT_CONST; 448 bits<4> CF_INST; 449 bits<1> WHOLE_QUAD_MODE; 450 bits<1> BARRIER; 451 452 let Word1{1-0} = KCACHE_MODE1; 453 let Word1{9-2} = KCACHE_ADDR0; 454 let Word1{17-10} = KCACHE_ADDR1; 455 let Word1{24-18} = COUNT; 456 let Word1{25} = ALT_CONST; 457 let Word1{29-26} = CF_INST; 458 let Word1{30} = WHOLE_QUAD_MODE; 459 let Word1{31} = BARRIER; 460} 461 462class CF_ALLOC_EXPORT_WORD0_RAT { 463 field bits<32> Word0; 464 465 bits<4> rat_id; 466 bits<6> rat_inst; 467 bits<2> rim; 468 bits<2> type; 469 bits<7> rw_gpr; 470 bits<1> rw_rel; 471 bits<7> index_gpr; 472 bits<2> elem_size; 473 474 let Word0{3-0} = rat_id; 475 let Word0{9-4} = rat_inst; 476 let Word0{10} = 0; // Reserved 477 let Word0{12-11} = rim; 478 let Word0{14-13} = type; 479 let Word0{21-15} = rw_gpr; 480 let Word0{22} = rw_rel; 481 let Word0{29-23} = index_gpr; 482 let Word0{31-30} = elem_size; 483} 484 485class CF_ALLOC_EXPORT_WORD1_BUF { 486 field bits<32> Word1; 487 488 bits<12> array_size; 489 bits<4> comp_mask; 490 bits<4> burst_count; 491 bits<1> vpm; 492 bits<1> eop; 493 bits<8> cf_inst; 494 bits<1> mark; 495 bits<1> barrier; 496 497 let Word1{11-0} = array_size; 498 let Word1{15-12} = comp_mask; 499 let Word1{19-16} = burst_count; 500 let Word1{20} = vpm; 501 let Word1{21} = eop; 502 let Word1{29-22} = cf_inst; 503 let Word1{30} = mark; 504 let Word1{31} = barrier; 505} 506