Searched refs:TX_CLK (Results 1 – 4 of 4) sorted by relevance
| /external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| D | ls1012a_serdes.c | 22 {0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
23 {0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
24 {0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
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| /external/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ |
| D | fsl_serdes.h | 144 TX_CLK, enumerator
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| /external/u-boot/arch/arm/dts/ |
| D | socfpga_arria10_socdk.dtsi | 74 * for TX_CLK on Arria 10.
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| /external/u-boot/drivers/video/ |
| D | Kconfig | 333 int "SSD2828 TX_CLK frequency (in MHz)"
342 parallel LCD interface instead of TX_CLK as the PLL clock source.
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