| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 34 class TargetRegisterClass {
39 typedef const TargetRegisterClass* const * sc_iterator;
47 TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts, in TargetRegisterClass() function
49 const TargetRegisterClass * const *supcs, in TargetRegisterClass()
50 const TargetRegisterClass * const *superregcs) in TargetRegisterClass()
54 virtual ~TargetRegisterClass() {} // Allow subclasses in ~TargetRegisterClass()
142 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
148 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
155 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
161 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 45 class TargetRegisterClass {
49 using sc_iterator = const TargetRegisterClass* const *;
110 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
115 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
122 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
127 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
222 using regclass_iterator = const TargetRegisterClass * const *;
314 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
320 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
326 unsigned getSpillAlignment(const TargetRegisterClass &RC) const { in getSpillAlignment()
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| D | RegisterClassInfo.h | 71 void compute(const TargetRegisterClass *RC) const;
74 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
90 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
97 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
107 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
123 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
131 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
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| D | RegisterScavenging.h | 32 class TargetRegisterClass; variable
126 BitVector getRegsAvailable(const TargetRegisterClass *RC);
130 unsigned FindUnusedReg(const TargetRegisterClass *RC) const;
161 unsigned scavengeRegister(const TargetRegisterClass *RC,
163 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister()
173 unsigned scavengeRegisterBackwards(const TargetRegisterClass &RC,
220 ScavengedInfo &spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 55 class TargetRegisterClass {
60 typedef const TargetRegisterClass* const * sc_iterator;
144 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
149 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
156 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
161 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
258 typedef const TargetRegisterClass * const * regclass_iterator;
343 const TargetRegisterClass *
348 const TargetRegisterClass *
349 getAllocatableClass(const TargetRegisterClass *RC) const;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 102 const TargetRegisterClass *getPointerRegClass(
129 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
132 bool isSGPRClass(const TargetRegisterClass *RC) const { in isSGPRClass()
142 const TargetRegisterClass *RC; in isSGPRReg()
151 bool hasVGPRs(const TargetRegisterClass *RC) const;
154 const TargetRegisterClass *getEquivalentVGPRClass(
155 const TargetRegisterClass *SRC) const;
158 const TargetRegisterClass *getEquivalentSGPRClass(
159 const TargetRegisterClass *VRC) const;
164 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 77 const TargetRegisterClass *getPointerRegClass(
90 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
93 bool isSGPRClass(const TargetRegisterClass *RC) const { in isSGPRClass()
103 const TargetRegisterClass *RC; in isSGPRReg()
112 bool hasVGPRs(const TargetRegisterClass *RC) const;
117 static bool isPseudoRegClass(const TargetRegisterClass *RC) { in isPseudoRegClass()
122 const TargetRegisterClass *getEquivalentVGPRClass(
123 const TargetRegisterClass *SRC) const;
126 const TargetRegisterClass *getEquivalentSGPRClass(
127 const TargetRegisterClass *VRC) const;
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| D | SIFixSGPRCopies.cpp | 128 static std::pair<const TargetRegisterClass *, const TargetRegisterClass *>
135 const TargetRegisterClass *SrcRC = in getCopyRegClasses()
143 const TargetRegisterClass *DstRC = in getCopyRegClasses()
151 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, in isVGPRToSGPRCopy()
152 const TargetRegisterClass *DstRC, in isVGPRToSGPRCopy()
157 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, in isSGPRToVGPRCopy()
158 const TargetRegisterClass *DstRC, in isSGPRToVGPRCopy()
193 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence()
220 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence()
225 const TargetRegisterClass *NewSrcRC = TRI->getEquivalentVGPRClass(SrcRC); in foldVGPRCopyIntoRegSequence()
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| /external/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 110 const TargetRegisterClass *
111 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { in getAllocatableClass()
117 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass()
127 const TargetRegisterClass *
133 const TargetRegisterClass* BestRC = nullptr; in getMinimalPhysRegClass()
135 const TargetRegisterClass* RC = *I; in getMinimalPhysRegClass()
148 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
156 const TargetRegisterClass *RC) const { in getAllocatableSet()
160 const TargetRegisterClass *SubClass = getAllocatableClass(RC); in getAllocatableSet()
178 const TargetRegisterClass *firstCommonClass(const uint32_t *A, in firstCommonClass()
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.h | 65 const TargetRegisterClass *
66 getMatchingSuperRegClass(const TargetRegisterClass *A,
67 const TargetRegisterClass *B,
70 const TargetRegisterClass *
71 getSubClassWithSubReg(const TargetRegisterClass *RC,
74 const TargetRegisterClass *
75 getLargestLegalSuperClass(const TargetRegisterClass *RC,
80 const TargetRegisterClass *
87 const TargetRegisterClass *
88 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.h | 65 const TargetRegisterClass *
66 getMatchingSuperRegClass(const TargetRegisterClass *A,
67 const TargetRegisterClass *B,
70 const TargetRegisterClass *
71 getSubClassWithSubReg(const TargetRegisterClass *RC,
74 const TargetRegisterClass *
75 getLargestLegalSuperClass(const TargetRegisterClass *RC,
80 const TargetRegisterClass *
87 const TargetRegisterClass *
88 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86RegisterInfo.h | 73 virtual const TargetRegisterClass *
74 getMatchingSuperRegClass(const TargetRegisterClass *A,
75 const TargetRegisterClass *B, unsigned Idx) const;
77 virtual const TargetRegisterClass *
78 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const;
80 const TargetRegisterClass*
81 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
85 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
90 const TargetRegisterClass *
91 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 173 const TargetRegisterClass *
174 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { in getAllocatableClass()
180 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass()
190 const TargetRegisterClass *
196 const TargetRegisterClass* BestRC = nullptr; in getMinimalPhysRegClass()
197 for (const TargetRegisterClass* RC : regclasses()) { in getMinimalPhysRegClass()
210 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
218 const TargetRegisterClass *RC) const { in getAllocatableSet()
222 const TargetRegisterClass *SubClass = getAllocatableClass(RC); in getAllocatableSet()
226 for (const TargetRegisterClass *C : regclasses()) in getAllocatableSet()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.h | 104 virtual const TargetRegisterClass *
105 getMatchingSuperRegClass(const TargetRegisterClass *A,
106 const TargetRegisterClass *B, unsigned Idx) const;
114 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
118 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
119 const TargetRegisterClass*
120 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
122 const TargetRegisterClass*
123 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
125 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | FastISel.h | 37 class TargetRegisterClass; variable
240 const TargetRegisterClass *RC);
246 const TargetRegisterClass *RC,
253 const TargetRegisterClass *RC,
261 const TargetRegisterClass *RC,
270 const TargetRegisterClass *RC,
278 const TargetRegisterClass *RC,
286 const TargetRegisterClass *RC,
294 const TargetRegisterClass *RC,
302 const TargetRegisterClass *RC,
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| D | RegisterScavenging.h | 28 class TargetRegisterClass; variable
52 const TargetRegisterClass *ScavengedRC;
103 BitVector getRegsAvailable(const TargetRegisterClass *RC);
107 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
118 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
120 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RenderMachineFunction.h | 32 class TargetRegisterClass; variable
43 bool operator()(const TargetRegisterClass *trc1, in operator()
44 const TargetRegisterClass *trc2) const { in operator()
51 typedef std::set<const TargetRegisterClass*, RegClassComp> RegClassSet;
151 unsigned getWorst(unsigned reg, const TargetRegisterClass *trc) const;
154 unsigned getCapacity(const TargetRegisterClass *trc) const;
158 unsigned getPressureAtSlot(const TargetRegisterClass *trc,
163 bool classOverCapacityAtSlot(const TargetRegisterClass *trc,
173 typedef std::map<const TargetRegisterClass*, unsigned> WorstMapLine;
174 typedef std::map<const TargetRegisterClass*, WorstMapLine> VRWorstMap;
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| D | CriticalAntiDepBreaker.cpp | 36 Classes(TRI->getNumRegs(), static_cast<const TargetRegisterClass *>(0)), in CriticalAntiDepBreaker()
47 Classes[i] = static_cast<const TargetRegisterClass *>(0); in StartBlock()
65 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
72 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
87 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
94 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
108 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
115 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
138 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in Observe()
145 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in Observe()
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| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetRegisterInfo.cpp | 54 const TargetRegisterClass *
60 const TargetRegisterClass* BestRC = 0; in getMinimalPhysRegClass()
62 const TargetRegisterClass* RC = *I; in getMinimalPhysRegClass()
75 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
82 const TargetRegisterClass *RC) const { in getAllocatableSet()
100 const TargetRegisterClass *
101 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A, in getCommonSubClass()
102 const TargetRegisterClass *B) const { in getCommonSubClass()
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 67 void compute(const TargetRegisterClass *RC) const;
70 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
93 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
103 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
119 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
127 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.h | 24 class TargetRegisterClass; variable
49 const TargetRegisterClass *
50 getSubClassWithSubReg(const TargetRegisterClass *RC,
73 const TargetRegisterClass *
76 const TargetRegisterClass *
77 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
105 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.h | 121 const TargetRegisterClass *
124 const TargetRegisterClass *
125 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
127 const TargetRegisterClass *
128 getLargestLegalSuperClass(const TargetRegisterClass *RC,
131 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
191 const TargetRegisterClass *SrcRC,
193 const TargetRegisterClass *DstRC,
195 const TargetRegisterClass *NewRC) const override;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.h | 135 const TargetRegisterClass *
138 const TargetRegisterClass *
139 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
141 const TargetRegisterClass *
142 getLargestLegalSuperClass(const TargetRegisterClass *RC,
145 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
206 const TargetRegisterClass *SrcRC,
208 const TargetRegisterClass *DstRC,
210 const TargetRegisterClass *NewRC,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.h | 66 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
67 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
68 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
76 unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
80 const TargetRegisterClass *RC) const;
84 const TargetRegisterClass *
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.h | 41 const TargetRegisterClass *
50 const TargetRegisterClass *
51 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
82 const TargetRegisterClass *SrcRC,
84 const TargetRegisterClass *DstRC,
86 const TargetRegisterClass *NewRC,
|