1 //===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef ARMBASEREGISTERINFO_H
15 #define ARMBASEREGISTERINFO_H
16
17 #include "ARM.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
19
20 #define GET_REGINFO_HEADER
21 #include "ARMGenRegisterInfo.inc"
22
23 namespace llvm {
24 class ARMSubtarget;
25 class ARMBaseInstrInfo;
26 class Type;
27
28 /// Register allocation hints.
29 namespace ARMRI {
30 enum {
31 RegPairOdd = 1,
32 RegPairEven = 2
33 };
34 }
35
36 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
37 /// or a stack/pc register that we should push/pop.
isARMArea1Register(unsigned Reg,bool isDarwin)38 static inline bool isARMArea1Register(unsigned Reg, bool isDarwin) {
39 using namespace ARM;
40 switch (Reg) {
41 case R0: case R1: case R2: case R3:
42 case R4: case R5: case R6: case R7:
43 case LR: case SP: case PC:
44 return true;
45 case R8: case R9: case R10: case R11:
46 // For darwin we want r7 and lr to be next to each other.
47 return !isDarwin;
48 default:
49 return false;
50 }
51 }
52
isARMArea2Register(unsigned Reg,bool isDarwin)53 static inline bool isARMArea2Register(unsigned Reg, bool isDarwin) {
54 using namespace ARM;
55 switch (Reg) {
56 case R8: case R9: case R10: case R11:
57 // Darwin has this second area.
58 return isDarwin;
59 default:
60 return false;
61 }
62 }
63
isARMArea3Register(unsigned Reg,bool isDarwin)64 static inline bool isARMArea3Register(unsigned Reg, bool isDarwin) {
65 using namespace ARM;
66 switch (Reg) {
67 case D15: case D14: case D13: case D12:
68 case D11: case D10: case D9: case D8:
69 return true;
70 default:
71 return false;
72 }
73 }
74
75 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
76 protected:
77 const ARMBaseInstrInfo &TII;
78 const ARMSubtarget &STI;
79
80 /// FramePtr - ARM physical register used as frame ptr.
81 unsigned FramePtr;
82
83 /// BasePtr - ARM physical register used as a base ptr in complex stack
84 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
85 /// variable size stack objects.
86 unsigned BasePtr;
87
88 // Can be only subclassed.
89 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
90 const ARMSubtarget &STI);
91
92 // Return the opcode that implements 'Op', or 0 if no opcode
93 unsigned getOpcode(int Op) const;
94
95 public:
96 /// Code Generation virtual methods...
97 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
98
99 BitVector getReservedRegs(const MachineFunction &MF) const;
100
101 /// getMatchingSuperRegClass - Return a subclass of the specified register
102 /// class A so that each register in it has a sub-register of the
103 /// specified sub-register index which is in the specified register class B.
104 virtual const TargetRegisterClass *
105 getMatchingSuperRegClass(const TargetRegisterClass *A,
106 const TargetRegisterClass *B, unsigned Idx) const;
107
108 /// canCombineSubRegIndices - Given a register class and a list of
109 /// subregister indices, return true if it's possible to combine the
110 /// subregister indices into one that corresponds to a larger
111 /// subregister. Return the new subregister index by reference. Note the
112 /// new index may be zero if the given subregisters can be combined to
113 /// form the whole register.
114 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
115 SmallVectorImpl<unsigned> &SubIndices,
116 unsigned &NewSubIdx) const;
117
118 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
119 const TargetRegisterClass*
120 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
121
122 const TargetRegisterClass*
123 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
124
125 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
126 MachineFunction &MF) const;
127
128 ArrayRef<unsigned> getRawAllocationOrder(const TargetRegisterClass *RC,
129 unsigned HintType, unsigned HintReg,
130 const MachineFunction &MF) const;
131
132 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
133 const MachineFunction &MF) const;
134
135 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
136 MachineFunction &MF) const;
137
138 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
139
140 bool hasBasePointer(const MachineFunction &MF) const;
141
142 bool canRealignStack(const MachineFunction &MF) const;
143 bool needsStackRealignment(const MachineFunction &MF) const;
144 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
145 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
146 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
147 unsigned BaseReg, int FrameIdx,
148 int64_t Offset) const;
149 void resolveFrameIndex(MachineBasicBlock::iterator I,
150 unsigned BaseReg, int64_t Offset) const;
151 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
152
153 bool cannotEliminateFrame(const MachineFunction &MF) const;
154
155 // Debug information queries.
156 unsigned getFrameRegister(const MachineFunction &MF) const;
getBaseRegister()157 unsigned getBaseRegister() const { return BasePtr; }
158
159 // Exception handling queries.
160 unsigned getEHExceptionRegister() const;
161 unsigned getEHHandlerRegister() const;
162
163 bool isLowRegister(unsigned Reg) const;
164
165
166 /// emitLoadConstPool - Emits a load from constpool to materialize the
167 /// specified immediate.
168 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
169 MachineBasicBlock::iterator &MBBI,
170 DebugLoc dl,
171 unsigned DestReg, unsigned SubIdx,
172 int Val,
173 ARMCC::CondCodes Pred = ARMCC::AL,
174 unsigned PredReg = 0,
175 unsigned MIFlags = MachineInstr::NoFlags)const;
176
177 /// Code Generation virtual methods...
178 virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
179
180 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
181
182 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
183
184 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
185
186 virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
187 MachineBasicBlock &MBB,
188 MachineBasicBlock::iterator I) const;
189
190 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
191 int SPAdj, RegScavenger *RS = NULL) const;
192
193 private:
194 unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
195
196 unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
197 };
198
199 } // end namespace llvm
200
201 #endif
202