| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb/ |
| D | segmented-stacks.ll | 1 …s -mtriple=thumb-linux-androideabi -verify-machineinstrs | FileCheck %s -check-prefix=Thumb-android
2 …-mtriple=thumb-linux-unknown-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=Thumb-linux
15 ; Thumb-android-LABEL: test_basic:
17 ; Thumb-android: push {r4, r5}
18 ; Thumb-android-NEXT: mov r5, sp
19 ; Thumb-android-NEXT: ldr r4, .LCPI0_0
20 ; Thumb-android-NEXT: ldr r4, [r4]
21 ; Thumb-android-NEXT: cmp r4, r5
22 ; Thumb-android-NEXT: blo .LBB0_2
24 ; Thumb-android: mov r4, #48
[all …]
|
| D | segmented-stacks-dynamic.ll | 1 …-mtriple=thumb-linux-unknown-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=Thumb-linux
2 …s -mtriple=thumb-linux-androideabi -verify-machineinstrs | FileCheck %s -check-prefix=Thumb-android
23 ; Thumb-linux: test_basic:
25 ; Thumb-linux: push {r4, r5}
26 ; Thumb-linux: mov r5, sp
27 ; Thumb-linux-NEXT: ldr r4, .LCPI0_0
28 ; Thumb-linux-NEXT: ldr r4, [r4]
29 ; Thumb-linux-NEXT: cmp r4, r5
30 ; Thumb-linux-NEXT: blo .LBB0_2
32 ; Thumb-linux: mov r4, #16
[all …]
|
| D | inlineasm-imm-thumb.ll | 3 ; Test Thumb-mode "I" constraint, for ADD immediate.
9 ; Test Thumb-mode "J" constraint, for negated ADD immediates.
15 ; Test Thumb-mode "K" constraint, for compatibility with GCC's internal use.
21 ; Test Thumb-mode "L" constraint, for 3-operand ADD immediates.
27 ; Test Thumb-mode "M" constraint, for "ADD r = sp + imm".
33 ; Test Thumb-mode "N" constraint, for values between 0 and 31.
39 ; Test Thumb-mode "O" constraint, for "ADD sp = sp + imm".
|
| /external/llvm/test/CodeGen/Thumb/ |
| D | segmented-stacks.ll | 1 …s -mtriple=thumb-linux-androideabi -verify-machineinstrs | FileCheck %s -check-prefix=Thumb-android
2 …-mtriple=thumb-linux-unknown-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=Thumb-linux
15 ; Thumb-android-LABEL: test_basic:
17 ; Thumb-android: push {r4, r5}
18 ; Thumb-android-NEXT: mov r5, sp
19 ; Thumb-android-NEXT: ldr r4, .LCPI0_0
20 ; Thumb-android-NEXT: ldr r4, [r4]
21 ; Thumb-android-NEXT: cmp r4, r5
22 ; Thumb-android-NEXT: blo .LBB0_2
24 ; Thumb-android: mov r4, #48
[all …]
|
| D | segmented-stacks-dynamic.ll | 1 …-mtriple=thumb-linux-unknown-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=Thumb-linux
2 …s -mtriple=thumb-linux-androideabi -verify-machineinstrs | FileCheck %s -check-prefix=Thumb-android
23 ; Thumb-linux: test_basic:
25 ; Thumb-linux: push {r4, r5}
26 ; Thumb-linux: mov r5, sp
27 ; Thumb-linux-NEXT: ldr r4, .LCPI0_0
28 ; Thumb-linux-NEXT: ldr r4, [r4]
29 ; Thumb-linux-NEXT: cmp r4, r5
30 ; Thumb-linux-NEXT: blo .LBB0_2
32 ; Thumb-linux: mov r4, #16
[all …]
|
| D | inlineasm-imm-thumb.ll | 3 ; Test Thumb-mode "I" constraint, for ADD immediate.
9 ; Test Thumb-mode "J" constraint, for negated ADD immediates.
15 ; Test Thumb-mode "K" constraint, for compatibility with GCC's internal use.
21 ; Test Thumb-mode "L" constraint, for 3-operand ADD immediates.
27 ; Test Thumb-mode "M" constraint, for "ADD r = sp + imm".
33 ; Test Thumb-mode "N" constraint, for values between 0 and 31.
39 ; Test Thumb-mode "O" constraint, for "ADD sp = sp + imm".
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | segmented-stacks.ll | 1 …b -mcpu=arm1156t2-s -mattr=+thumb2 -verify-machineinstrs | FileCheck %s -check-prefix=Thumb-android
13 ; Thumb-android: test_basic:
15 ; Thumb-android: push {r4, r5}
16 ; Thumb-android-NEXT: mrc p15, #0, r4, c13, c0, #3
17 ; Thumb-android-NEXT: mov r5, sp
18 ; Thumb-android-NEXT: ldr r4, [r4, #252]
19 ; Thumb-android-NEXT: cmp r4, r5
20 ; Thumb-android-NEXT: blo .LBB0_2
22 ; Thumb-android: mov r4, #48
23 ; Thumb-android-NEXT: mov r5, #0
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/ |
| D | segmented-stacks.ll | 1 …i -mcpu=arm1156t2-s -mattr=+thumb2 -verify-machineinstrs | FileCheck %s -check-prefix=Thumb-android
13 ; Thumb-android: test_basic:
15 ; Thumb-android: push {r4, r5}
16 ; Thumb-android-NEXT: mrc p15, #0, r4, c13, c0, #3
17 ; Thumb-android-NEXT: mov r5, sp
18 ; Thumb-android-NEXT: ldr r4, [r4, #252]
19 ; Thumb-android-NEXT: cmp r4, r5
20 ; Thumb-android-NEXT: blo .LBB0_2
22 ; Thumb-android: mov r4, #48
23 ; Thumb-android-NEXT: mov r5, #0
[all …]
|
| /external/llvm/test/MC/ARM/ |
| D | directive-arch-mode-switch.s | 8 @ In ARM mode, switch to an arch which has ARM and Thumb, no warning or .code directive (stay in AR…
15 @ In ARM mode, switch to an arch which has Thumb only, expect warning and .code 16 directive
21 @ In Thumb mode, switch to an arch which has ARM and Thumb, no warning or .code directive (stay in …
28 @ In Thumb mode, switch to a CPU which has ARM and Thumb, no warning or .code directive (stay in Th…
39 @ In ARM mode, switch to a CPU which has ARM and Thumb, no warning or .code directive (stay in ARM …
46 @ In ARM mode, switch to a CPU which has Thumb only, expect warning and .code 16 directive
52 @ We don't have any ARM-only targets (i.e. v4), so we can't test the forced Thumb->ARM case
|
| D | ldr-pseudo-cond.s | 29 @ Can use the narrow Thumb mov as it does not set flags in an IT block
34 @ Must use the wide Thumb mov if the constant can't be represented
|
| D | ldr-pseudo-cond-darwin.s | 29 @ Can use the narrow Thumb mov as it does not set flags in an IT block
34 @ Must use the wide Thumb mov if the constant can't be represented
|
| D | arm-thumb-cpus.s | 30 @ CHECK-ARM-ONLY: target does not support Thumb mode
31 @ CHECK-ARM-ONLY: target does not support Thumb mode
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | directive-arch-mode-switch.s | 8 @ In ARM mode, switch to an arch which has ARM and Thumb, no warning or .code directive (stay in AR…
15 @ In ARM mode, switch to an arch which has Thumb only, expect warning and .code 16 directive
21 @ In Thumb mode, switch to an arch which has ARM and Thumb, no warning or .code directive (stay in …
28 @ In Thumb mode, switch to a CPU which has ARM and Thumb, no warning or .code directive (stay in Th…
39 @ In ARM mode, switch to a CPU which has ARM and Thumb, no warning or .code directive (stay in ARM …
46 @ In ARM mode, switch to a CPU which has Thumb only, expect warning and .code 16 directive
52 @ We don't have any ARM-only targets (i.e. v4), so we can't test the forced Thumb->ARM case
|
| D | ldr-pseudo-cond.s | 29 @ Can use the narrow Thumb mov as it does not set flags in an IT block
34 @ Must use the wide Thumb mov if the constant can't be represented
|
| D | ldr-pseudo-cond-darwin.s | 29 @ Can use the narrow Thumb mov as it does not set flags in an IT block
34 @ Must use the wide Thumb mov if the constant can't be represented
|
| /external/ImageMagick/www/Magick++/ |
| D | thumbnail-anatomy-framed.fig | 30 4 1 -1 0 0 16 10 0.0000 4 120 480 5775 975 Thumb\001
33 4 1 -1 0 0 16 10 0.0000 4 120 480 3825 975 Thumb\001
36 4 1 -1 0 0 16 10 0.0000 4 120 480 4800 975 Thumb\001
37 4 1 -1 0 0 16 10 0.0000 4 120 480 6900 3000 Thumb\001
39 4 1 -1 0 0 16 10 0.0000 4 120 480 6900 4200 Thumb\001
|
| D | thumbnail-anatomy-plain.fig | 28 4 1 -1 0 0 16 10 0.0000 4 120 480 3825 975 Thumb\001
31 4 1 -1 0 0 16 10 0.0000 4 120 480 4950 975 Thumb\001
33 4 1 -1 0 0 16 10 0.0000 4 120 480 6300 3000 Thumb\001
35 4 1 -1 0 0 16 10 0.0000 4 120 480 6300 3825 Thumb\001
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb/ |
| D | inlineasm-imm-thumb.ll | 3 ; Test Thumb-mode "I" constraint, for ADD immediate.
9 ; Test Thumb-mode "J" constraint, for negated ADD immediates.
15 ; Test Thumb-mode "K" constraint, for compatibility with GCC's internal use.
21 ; Test Thumb-mode "L" constraint, for 3-operand ADD immediates.
27 ; Test Thumb-mode "M" constraint, for "ADD r = sp + imm".
33 ; Test Thumb-mode "N" constraint, for values between 0 and 31.
39 ; Test Thumb-mode "O" constraint, for "ADD sp = sp + imm".
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Linker/ |
| D | link-arm-and-thumb-module-inline-asm.ll | 1 ; This test checks that proper directives to switch between ARM and Thumb mode
2 ; are added when linking ARM and Thumb modules.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | README-Thumb.txt | 2 // Random ideas for the ARM backend (Thumb specific).
5 * Add support for compiling functions in both ARM and Thumb mode, then taking
12 * Thumb doesn't have normal pre/post increment addressing modes, but you can
32 * Thumb jumptable codegen can improve given some help from the assembler. This
214 etc. Almost all Thumb instructions clobber condition code.
218 Thumb load / store address mode offsets are scaled. The values kept in the
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | README-Thumb.txt | 2 // Random ideas for the ARM backend (Thumb specific).
5 * Add support for compiling functions in both ARM and Thumb mode, then taking
12 * Thumb doesn't have normal pre/post increment addressing modes, but you can
32 * Thumb jumptable codegen can improve given some help from the assembler. This
216 etc. Almost all Thumb instructions clobber condition code.
224 Thumb load / store address mode offsets are scaled. The values kept in the
|
| /external/llvm/lib/Target/ARM/ |
| D | README-Thumb.txt | 2 // Random ideas for the ARM backend (Thumb specific).
5 * Add support for compiling functions in both ARM and Thumb mode, then taking
12 * Thumb doesn't have normal pre/post increment addressing modes, but you can
32 * Thumb jumptable codegen can improve given some help from the assembler. This
214 etc. Almost all Thumb instructions clobber condition code.
218 Thumb load / store address mode offsets are scaled. The values kept in the
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | fast-isel-ext.ll | 5 ; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports
6 ; Thumb2. The ARMFastISel::ARMEmitIntExt code should work for Thumb by always
9 ; Note that lsl, asr and lsr in Thumb are all encoded as 16-bit instructions
|
| D | gpr-paired-spill-thumbinst.ll | 4 ; This test makes sure spills of 64-bit pairs in Thumb mode actually
17 ; Make sure we are actually creating the Thumb versions of the spill
|
| /external/llvm/test/CodeGen/ARM/ |
| D | fast-isel-ext.ll | 5 ; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports
6 ; Thumb2. The ARMFastISel::ARMEmitIntExt code should work for Thumb by always
9 ; Note that lsl, asr and lsr in Thumb are all encoded as 16-bit instructions
|