1@ RUN: llvm-mc -triple arm-none-eabi -filetype asm %s 2>%t | FileCheck %s 2@ RUN: FileCheck %s <%t --check-prefix=STDERR 3 4@ Start in arm mode 5 .arm 6@ CHECK: .code 32 7 8@ In ARM mode, switch to an arch which has ARM and Thumb, no warning or .code directive (stay in ARM mode) 9 .arch armv7-a 10@ STDERR-NOT: [[@LINE-1]]:{{[0-9]+}}: warning: 11@ CHECK-NOT: .code 12@ CHECK: .arch armv7-a 13@ CHECK-NOT: .code 14 15@ In ARM mode, switch to an arch which has Thumb only, expect warning and .code 16 directive 16 .arch armv6-m 17@ STDERR: [[@LINE-1]]:{{[0-9]+}}: warning: new target does not support arm mode, switching to thumb mode 18@ CHECK: .code 16 19@ CHECK: .arch armv6-m 20 21@ In Thumb mode, switch to an arch which has ARM and Thumb, no warning or .code directive (stay in Thumb mode) 22 .arch armv7-a 23@ STDERR-NOT: [[@LINE-1]]:{{[0-9]+}}: warning: 24@ CHECK-NOT: .code 25@ CHECK: .arch armv7-a 26@ CHECK-NOT: .code 27 28@ In Thumb mode, switch to a CPU which has ARM and Thumb, no warning or .code directive (stay in Thumb mode) 29 .cpu cortex-a8 30@ STDERR-NOT: [[@LINE-1]]:{{[0-9]+}}: warning: 31@ CHECK-NOT: .code 32@ CHECK: .cpu cortex-a8 33@ CHECK-NOT: .code 34 35@ Switch to ARM mode 36 .arm 37@ CHECK: .code 32 38 39@ In ARM mode, switch to a CPU which has ARM and Thumb, no warning or .code directive (stay in ARM mode) 40 .cpu cortex-a8 41@ STDERR-NOT: [[@LINE-1]]:{{[0-9]+}}: warning: 42@ CHECK-NOT: .code 43@ CHECK: .cpu cortex-a8 44@ CHECK-NOT: .code 45 46@ In ARM mode, switch to a CPU which has Thumb only, expect warning and .code 16 directive 47 .cpu cortex-m3 48@ STDERR: [[@LINE-1]]:{{[0-9]+}}: warning: new target does not support arm mode, switching to thumb mode 49@ CHECK: .cpu cortex-m3 50@ CHECK: .code 16 51 52@ We don't have any ARM-only targets (i.e. v4), so we can't test the forced Thumb->ARM case 53