| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 1331 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in SelectAtomic64() local
1332 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) in SelectAtomic64()
1336 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain}; in SelectAtomic64()
1359 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in SelectAtomicLoadAdd() local
1360 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) in SelectAtomicLoadAdd()
1482 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain }; in SelectAtomicLoadAdd()
1488 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain }; in SelectAtomicLoadAdd()
1571 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in SelectAtomicLoadArith() local
1572 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) in SelectAtomicLoadArith()
1643 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain }; in SelectAtomicLoadArith()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 623 SDValue Tmp0, Tmp1, Tmp2; in Select() local
624 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2); in Select()
644 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) }; in Select()
705 SDValue Tmp0, Tmp1, Tmp2; in Select() local
706 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2); in Select()
729 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) }; in Select()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 244 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
245 Tmp0 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
256 Tmp0 = InReg; in LowerFPToInt()
258 BuildMI(BB, DL, TII.get(Abs), Tmp0) in LowerFPToInt()
264 .addReg(Tmp0) in LowerFPToInt()
275 .addReg(Tmp0) in LowerFPToInt()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUPromoteAlloca.cpp | 709 Value *Tmp0 = Builder.CreateMul(TCntY, TCntZ, "", true, true); in handleAlloca() local
710 Tmp0 = Builder.CreateMul(Tmp0, TIdX); in handleAlloca()
712 Value *TID = Builder.CreateAdd(Tmp0, Tmp1); in handleAlloca()
|
| D | AMDGPUISelLowering.cpp | 1460 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT), in LowerUDIVREM() local
1464 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num); in LowerUDIVREM()
1676 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); in LowerFTRUNC() local
1686 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC()
1783 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M); in LowerFROUND64() local
1785 DAG.getConstant(0, SL, MVT::i64), Tmp0, in LowerFROUND64()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUPromoteAlloca.cpp | 789 Value *Tmp0 = Builder.CreateMul(TCntY, TCntZ, "", true, true); in handleAlloca() local
790 Tmp0 = Builder.CreateMul(Tmp0, TIdX); in handleAlloca()
792 Value *TID = Builder.CreateAdd(Tmp0, Tmp1); in handleAlloca()
|
| D | AMDGPUCodeGenPrepare.cpp | 695 Value *Tmp0 = Builder.CreateSelect(RCP_HI_0_CC, RCP_A_E, RCP_S_E); in expandDivRem32() local
698 Value *Quotient = getMulHu(Builder, Tmp0, Num); in expandDivRem32()
|
| D | AMDGPUISelLowering.cpp | 1810 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT), in LowerUDIVREM() local
1814 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num); in LowerUDIVREM()
2026 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); in LowerFTRUNC() local
2036 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC()
2138 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M); in LowerFROUND64() local
2140 DAG.getConstant(0, SL, MVT::i64), Tmp0, in LowerFROUND64()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2625 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
2627 tryFoldVecLoad(Node, N1.getNode(), N1.getOperand(0), Tmp0, Tmp1, Tmp2, in emitPCMPISTR()
2630 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPISTR()
2664 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
2666 tryFoldVecLoad(Node, N2.getNode(), N2.getOperand(0), Tmp0, Tmp1, Tmp2, in emitPCMPESTR()
2669 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPESTR()
2986 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
2987 bool foldedLoad = tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2990 foldedLoad = tryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
3002 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), in Select()
[all …]
|
| D | X86ISelLowering.cpp | 29059 unsigned Tmp0 = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1); in ComputeNumSignBitsForTargetNode() local
29061 unsigned Tmp = std::min(Tmp0, Tmp1); in ComputeNumSignBitsForTargetNode()
29097 unsigned Tmp0 = DAG.ComputeNumSignBits(Op.getOperand(0), Depth+1); in ComputeNumSignBitsForTargetNode() local
29098 if (Tmp0 == 1) return 1; // Early out. in ComputeNumSignBitsForTargetNode()
29100 return std::min(Tmp0, Tmp1); in ComputeNumSignBitsForTargetNode()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2211 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
2212 bool foldedLoad = tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2215 foldedLoad = tryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2227 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), in Select()
2364 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
2365 bool foldedLoad = tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2372 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain; in Select() local
2373 if (tryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in Select()
2374 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) }; in Select()
2428 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), in Select()
|
| /external/webrtc/webrtc/modules/audio_coding/codecs/isac/main/source/ |
| D | structs.h | 252 double Tmp0[MAXFFTSIZE]; member
|
| D | fft.c | 340 Rtmp = (REAL *) fftstate->Tmp0; in FFTRADIX()
|
| /external/llvm/lib/Transforms/Utils/ |
| D | IntegerDivision.cpp | 255 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); in generateUnsignedDivisionCode() local
257 Value *SR = Builder.CreateSub(Tmp0, Tmp1); in generateUnsignedDivisionCode()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Utils/ |
| D | IntegerDivision.cpp | 255 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); in generateUnsignedDivisionCode() local
257 Value *SR = Builder.CreateSub(Tmp0, Tmp1); in generateUnsignedDivisionCode()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 3086 SDValue Tmp0 = Op.getOperand(0); in LowerFCOPYSIGN() local
3091 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || in LowerFCOPYSIGN()
3092 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
3106 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); in LowerFCOPYSIGN()
3117 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
3128 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); in LowerFCOPYSIGN()
3151 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFCOPYSIGN()
3152 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); in LowerFCOPYSIGN()
3154 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); in LowerFCOPYSIGN()
3158 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4244 SDValue Tmp0 = Op.getOperand(0); in LowerFCOPYSIGN() local
4249 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || in LowerFCOPYSIGN()
4250 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
4264 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); in LowerFCOPYSIGN()
4275 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
4286 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); in LowerFCOPYSIGN()
4309 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFCOPYSIGN()
4310 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); in LowerFCOPYSIGN()
4312 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); in LowerFCOPYSIGN()
4316 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4917 SDValue Tmp0 = Op.getOperand(0); in LowerFCOPYSIGN() local
4922 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || in LowerFCOPYSIGN()
4923 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
4937 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); in LowerFCOPYSIGN()
4948 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
4959 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); in LowerFCOPYSIGN()
4982 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFCOPYSIGN()
4983 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); in LowerFCOPYSIGN()
4985 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); in LowerFCOPYSIGN()
4989 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
[all …]
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 6182 SDValue Tmp0 = getValue(I.getArgOperand(0)); in visitBinaryFloatCall() local
6184 EVT VT = Tmp0.getValueType(); in visitBinaryFloatCall()
6185 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1)); in visitBinaryFloatCall()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 6841 SDValue Tmp0 = getValue(I.getArgOperand(0)); in visitBinaryFloatCall() local
6843 EVT VT = Tmp0.getValueType(); in visitBinaryFloatCall()
6844 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1)); in visitBinaryFloatCall()
|