| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/ |
| D | udivrem-change-width.ll | 57 ; CHECK-NEXT: [[UDIV:%.*]] = zext i8 [[DIV]] to i32
58 ; CHECK-NEXT: ret i32 [[UDIV]]
69 ; CHECK-NEXT: [[UDIV:%.*]] = zext <2 x i8> [[DIV]] to <2 x i32>
70 ; CHECK-NEXT: ret <2 x i32> [[UDIV]]
82 ; CHECK-NEXT: [[UDIV:%.*]] = udiv i32 [[ZA]], [[ZB]]
84 ; CHECK-NEXT: [[R:%.*]] = mul nuw nsw i32 [[UDIV]], [[EXTRA_USES]]
98 ; CHECK-NEXT: [[UDIV:%.*]] = zext i9 [[DIV]] to i32
99 ; CHECK-NEXT: ret i32 [[UDIV]]
163 ; CHECK-NEXT: [[UDIV:%.*]] = zext i8 [[DIV]] to i32
164 ; CHECK-NEXT: ret i32 [[UDIV]]
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 427 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
431 { ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
435 { ISD::UDIV, MVT::v4i16, ReciprocalDivCost}, in getArithmeticInstrCost()
439 { ISD::UDIV, MVT::v8i8, ReciprocalDivCost}, in getArithmeticInstrCost()
444 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
448 { ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
452 { ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
456 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 472 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
476 { ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
480 { ISD::UDIV, MVT::v4i16, ReciprocalDivCost}, in getArithmeticInstrCost()
484 { ISD::UDIV, MVT::v8i8, ReciprocalDivCost}, in getArithmeticInstrCost()
489 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
493 { ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
497 { ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
501 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | legalize-div.mir | 45 ; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
46 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
|
| D | legalize-rem.mir | 38 ; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]
39 ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[UDIV]], [[COPY1]]
|
| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 122 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
124 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
228 { ISD::UDIV, MVT::v32i8, 32*20 }, in getArithmeticInstrCost()
229 { ISD::UDIV, MVT::v16i16, 16*20 }, in getArithmeticInstrCost()
230 { ISD::UDIV, MVT::v8i32, 8*20 }, in getArithmeticInstrCost()
231 { ISD::UDIV, MVT::v4i64, 4*20 }, in getArithmeticInstrCost()
274 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence in getArithmeticInstrCost()
276 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence in getArithmeticInstrCost()
358 { ISD::UDIV, MVT::v16i8, 16*20 }, in getArithmeticInstrCost()
359 { ISD::UDIV, MVT::v8i16, 8*20 }, in getArithmeticInstrCost()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | urem-opt-size.ll | 6 ; When the processor features hardware division, UDIV + UREM can be turned
7 ; into UDIV + MLS. This prevents the library function __aeabi_uidivmod to be
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiTargetTransformInfo.h | 72 case ISD::UDIV:
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiTargetTransformInfo.h | 94 case ISD::UDIV:
|
| /external/compiler-rt/lib/builtins/arm/ |
| D | umodsi3.S | 78 # error THUMB mode requires CLZ or UDIV
|
| D | udivsi3.S | 82 # error THUMB mode requires CLZ or UDIV
|
| D | udivmodsi4.S | 82 # error THUMB mode requires CLZ or UDIV
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 189 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 138 OP12(UDIV)
|
| D | tgsi_info_opcodes.h | 131 OPCODE(1, 2, COMP, UDIV)
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 201 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
|
| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 166 OP12(UDIV)
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 148 case ISD::UDIV: { in Select()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 247 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || in getArithmeticInstrCost()
278 if (ISD == ISD::UDIV) in getArithmeticInstrCost()
296 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
314 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
334 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
338 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
362 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. in getArithmeticInstrCost()
364 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence in getArithmeticInstrCost()
370 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. in getArithmeticInstrCost()
372 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence in getArithmeticInstrCost()
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 85 setOperationAction(ISD::UDIV, MVT::i16, Expand); in BlackfinTargetLowering()
86 setOperationAction(ISD::UDIV, MVT::i32, Expand); in BlackfinTargetLowering()
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-rm-a32.json | 62 "Udiv", // UDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
|
| D | cond-rd-rn-rm-t32.json | 61 "Udiv", // UDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelLowering.cpp | 100 setOperationAction(ISD::UDIV , MVT::i64, Custom); in AlphaTargetLowering()
692 case ISD::UDIV: in LowerOperation()
701 case ISD::UDIV: opstr = "__divqu"; break; in LowerOperation()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 342 case ISD::UDIV: { in Select()
|