1// Copyright 2016, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright notice, 10// this list of conditions and the following disclaimer in the documentation 11// and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may be 13// used to endorse or promote products derived from this software without 14// specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27// Test description for instructions with the following operands: 28// MNEMONIC<c> <rd>, <rn>, <rm> 29// 30// The instructions covered in this test do not write to the `Q` and `GE` flags, 31// these are covered in other description files. 32 33{ 34 "mnemonics": [ 35 "Mul", // MUL{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; A1 36 "Muls", // MULS{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; A1 37 "Qadd16", // QADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 38 "Qadd8", // QADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 39 "Qasx", // QASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 40 "Qsax", // QSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 41 "Qsub16", // QSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 42 "Qsub8", // QSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 43 "Sdiv", // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 44 "Shadd16", // SHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 45 "Shadd8", // SHADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 46 "Shasx", // SHASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 47 "Shsax", // SHSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 48 "Shsub16", // SHSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 49 "Shsub8", // SHSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 50 "Smmul", // SMMUL{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 51 "Smmulr", // SMMULR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 52 "Smuad", // SMUAD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 53 "Smuadx", // SMUADX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 54 "Smulbb", // SMULBB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 55 "Smulbt", // SMULBT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 56 "Smultb", // SMULTB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 57 "Smultt", // SMULTT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 58 "Smulwb", // SMULWB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 59 "Smulwt", // SMULWT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 60 "Smusd", // SMUSD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 61 "Smusdx", // SMUSDX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 62 "Udiv", // UDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 63 "Uhadd16", // UHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 64 "Uhadd8", // UHADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 65 "Uhasx", // UHASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 66 "Uhsax", // UHSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 67 "Uhsub16", // UHSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 68 "Uhsub8", // UHSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 69 "Uqadd16", // UQADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 70 "Uqadd8", // UQADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 71 "Uqasx", // UQASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 72 "Uqsax", // UQSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 73 "Uqsub16", // UQSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 74 "Uqsub8", // UQSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 75 "Usad8", // USAD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 76 77 // Instructions affecting the GE bits. 78 "Sadd16", // SADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 79 "Sadd8", // SADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 80 "Sasx", // SASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 81 "Sel", // SEL{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 82 "Ssax", // SSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 83 "Ssub16", // SSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 84 "Ssub8", // SSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 85 "Uadd16", // UADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 86 "Uadd8", // UADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 87 "Uasx", // UASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 88 "Usax", // USAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 89 "Usub16", // USUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 90 "Usub8", // USUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1 91 92 // Instructions affecting the Q bit. 93 "Qadd", // QADD{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; A1 94 "Qdadd", // QDADD{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; A1 95 "Qdsub", // QDSUB{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; A1 96 "Qsub" // QSUB{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; A1 97 ], 98 "description": { 99 "operands": [ 100 { 101 "name": "cond", 102 "type": "Condition" 103 }, 104 { 105 "name": "rd", 106 "type": "AllRegistersButPC" 107 }, 108 { 109 "name": "rn", 110 "type": "AllRegistersButPC" 111 }, 112 { 113 "name": "rm", 114 "type": "AllRegistersButPC" 115 } 116 ], 117 "inputs": [ 118 { 119 "name": "apsr", 120 "type": "NZCV" 121 }, 122 { 123 "name": "qbit", 124 "type": "Q" 125 }, 126 { 127 "name": "ge", 128 "type": "GE" 129 }, 130 { 131 "name": "rd", 132 "type": "Register" 133 }, 134 { 135 "name": "rn", 136 "type": "Register" 137 }, 138 { 139 "name": "rm", 140 "type": "Register" 141 } 142 ] 143 }, 144 "test-files": [ 145 { 146 "type": "assembler", 147 "test-cases": [ 148 { 149 "name": "Operands", 150 "operands": [ 151 "cond", "rd", "rn", "rm" 152 ], 153 "operand-limit": 300 154 } 155 ] 156 }, 157 { 158 "type": "simulator", 159 "test-cases": [ 160 { 161 "name": "Condition", 162 "operands": [ 163 "cond" 164 ], 165 "inputs": [ 166 "apsr" 167 ] 168 }, 169 { 170 "name": "RdIsRnIsRm", 171 "operands": [ 172 "rd", "rn", "rm" 173 ], 174 "inputs": [ 175 "rd", "rn", "rm" 176 ], 177 "operand-filter": "(rd == rn) and (rd == rm)", 178 "input-filter": "(rd == rn) and (rd == rm)" 179 }, 180 { 181 "name": "RdIsRn", 182 "operands": [ 183 "rd", "rn", "rm" 184 ], 185 "inputs": [ 186 "rd", "rn", "rm" 187 ], 188 "operand-filter": "(rd == rn) and (rn != rm)", 189 "operand-limit": 10, 190 "input-filter": "rd == rn", 191 "input-limit": 200 192 }, 193 { 194 "name": "RdIsRm", 195 "operands": [ 196 "rd", "rn", "rm" 197 ], 198 "inputs": [ 199 "rd", "rn", "rm" 200 ], 201 "operand-filter": "(rd == rm) and (rn != rm)", 202 "operand-limit": 10, 203 "input-filter": "rd == rm", 204 "input-limit": 200 205 }, 206 { 207 "name": "RnIsRm", 208 "operands": [ 209 "rd", "rn", "rm" 210 ], 211 "inputs": [ 212 "rd", "rn", "rm" 213 ], 214 "operand-filter": "(rn == rm) and (rm != rd)", 215 "operand-limit": 10, 216 "input-filter": "rn == rm", 217 "input-limit": 200 218 }, 219 { 220 "name": "RdIsNotRnIsNotRm", 221 "operands": [ 222 "rd", "rn", "rm" 223 ], 224 "inputs": [ 225 "rd", "rn", "rm" 226 ], 227 "operand-filter": "(rd != rn) and (rd != rm)", 228 "operand-limit": 10, 229 "input-limit": 200 230 } 231 ] 232 }, 233 { 234 "name": "ge", 235 "type": "simulator", 236 "mnemonics": [ 237 "Sadd16", 238 "Sadd8", 239 "Sasx", 240 "Ssax", 241 "Ssub16", 242 "Ssub8", 243 "Uadd16", 244 "Uadd8", 245 "Uasx", 246 "Usax", 247 "Usub16", 248 "Usub8" 249 ], 250 "test-cases": [ 251 { 252 "name": "GE", 253 "operands": [ 254 "rd", "rn", "rm" 255 ], 256 "inputs": [ 257 "ge", "rn", "rm" 258 ], 259 "operand-filter": "(rd != rn) and (rn != rm)", 260 "operand-limit": 1, 261 // Only use "all set" and "all cleared" as inputs. 262 "input-filter": "ge == 'NoFlag' or ge == 'GE0123Flag'", 263 "input-limit": 200 264 } 265 ] 266 }, 267 { 268 "name": "sel", 269 "type": "simulator", 270 "mnemonics": [ 271 "Sel" 272 ], 273 "test-cases": [ 274 { 275 "name": "GE", 276 "operands": [ 277 "rd", "rn", "rm" 278 ], 279 "inputs": [ 280 "ge", "rn", "rm" 281 ], 282 "operand-filter": "(rd != rn) and (rn != rm)", 283 "operand-limit": 1, 284 "input-limit": 200 285 } 286 ] 287 }, 288 { 289 "name": "q", 290 "type": "simulator", 291 "mnemonics": [ 292 "Qadd", 293 "Qdadd", 294 "Qdsub", 295 "Qsub" 296 ], 297 "test-cases": [ 298 { 299 "name": "QOutput", 300 "operands": [ 301 "rn", "rm" 302 ], 303 "inputs": [ 304 "qbit", "rn", "rm" 305 ], 306 "operand-limit": 1, 307 "operand-filter": "rn != rm", 308 "input-limit": 200 309 } 310 ] 311 } 312 ] 313} 314