| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/ |
| D | udivrem-change-width.ll | 110 ; CHECK-NEXT: [[UREM:%.*]] = zext i8 [[TMP1]] to i32
111 ; CHECK-NEXT: ret i32 [[UREM]]
122 ; CHECK-NEXT: [[UREM:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32>
123 ; CHECK-NEXT: ret <2 x i32> [[UREM]]
135 ; CHECK-NEXT: [[UREM:%.*]] = urem i32 [[ZA]], [[ZB]]
137 ; CHECK-NEXT: [[R:%.*]] = mul nuw nsw i32 [[UREM]], [[EXTRA_USES]]
151 ; CHECK-NEXT: [[UREM:%.*]] = zext i9 [[TMP1]] to i32
152 ; CHECK-NEXT: ret i32 [[UREM]]
209 ; CHECK-NEXT: [[UREM:%.*]] = zext i8 [[TMP1]] to i32
210 ; CHECK-NEXT: ret i32 [[UREM]]
[all …]
|
| D | add4.ll | 8 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[X:%.*]], 19136
9 ; CHECK-NEXT: ret i64 [[UREM]]
23 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[X:%.*]], 576
24 ; CHECK-NEXT: ret i64 [[UREM]]
|
| D | rem.ll | 328 ; CHECK-NEXT: [[UREM:%.*]] = and i64 [[TMP1]], [[X:%.*]]
329 ; CHECK-NEXT: ret i64 [[UREM]]
342 ; CHECK-NEXT: [[UREM:%.*]] = zext i32 [[TMP2]] to i64
343 ; CHECK-NEXT: ret i64 [[UREM]]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 429 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
433 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
437 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
441 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
446 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
450 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
454 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
458 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 474 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
478 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
482 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
486 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
491 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
495 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
499 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
503 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiTargetTransformInfo.h | 73 case ISD::UREM:
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiTargetTransformInfo.h | 95 case ISD::UREM:
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 189 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 201 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 248 ISD == ISD::UREM) && in getArithmeticInstrCost()
283 if (ISD == ISD::UREM) in getArithmeticInstrCost()
297 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
315 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
335 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
339 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
363 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. in getArithmeticInstrCost()
365 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence in getArithmeticInstrCost()
371 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. in getArithmeticInstrCost()
373 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelLowering.cpp | 98 setOperationAction(ISD::UREM , MVT::i64, Custom); in AlphaTargetLowering()
678 case ISD::UREM: in LowerOperation()
683 SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ? in LowerOperation()
699 case ISD::UREM: opstr = "__remqu"; break; in LowerOperation()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 89 setOperationAction(ISD::UREM, MVT::i16, Expand); in BlackfinTargetLowering()
90 setOperationAction(ISD::UREM, MVT::i32, Expand); in BlackfinTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | urem-opt-size.ll | 6 ; When the processor features hardware division, UDIV + UREM can be turned
|
| D | divmod-eabi.ll | 12 ; All "eabi" (Bare, GNU and Android) must lower SREM/UREM to __aeabi_{u,i}divmod
|
| /external/llvm/test/CodeGen/ARM/ |
| D | divmod-eabi.ll | 3 ; All "eabi" (Bare, GNU and Android) must lower SREM/UREM to __aeabi_{u,i}divmod
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1679 case ISD::UREM: in selectDivRem()
1696 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
1803 if (!selectBinaryOp(I, ISD::UREM)) in fastSelectInstruction()
1804 return selectDivRem(I, ISD::UREM); in fastSelectInstruction()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 145 case ISD::UREM: in LegalizeOp()
|
| D | SelectionDAGBuilder.h | 484 void visitURem(const User &I) { visitBinary(I, ISD::UREM); } in visitURem()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1905 case ISD::UREM: in selectDivRem()
1922 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
2027 if (!selectBinaryOp(I, ISD::UREM)) in fastSelectInstruction()
2028 return selectDivRem(I, ISD::UREM); in fastSelectInstruction()
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 103 setOperationAction(ISD::UREM, MVT::i32, Expand); in SystemZTargetLowering()
105 setOperationAction(ISD::UREM, MVT::i64, Expand); in SystemZTargetLowering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 181 setOperationAction(ISD::UREM, MVT::i8, Expand); in SPUTargetLowering()
187 setOperationAction(ISD::UREM, MVT::i16, Expand); in SPUTargetLowering()
193 setOperationAction(ISD::UREM, MVT::i32, Expand); in SPUTargetLowering()
199 setOperationAction(ISD::UREM, MVT::i64, Expand); in SPUTargetLowering()
205 setOperationAction(ISD::UREM, MVT::i128, Expand); in SPUTargetLowering()
425 setOperationAction(ISD::UREM, VT, Expand); in SPUTargetLowering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 155 setOperationAction(ISD::UREM, MVT::i8, Expand); in MSP430TargetLowering()
161 setOperationAction(ISD::UREM, MVT::i16, Expand); in MSP430TargetLowering()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 183 case ISD::UREM: return "urem"; in getOperationName()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 148 setOperationAction(ISD::UREM, MVT::i8, Expand); in MSP430TargetLowering()
154 setOperationAction(ISD::UREM, MVT::i16, Expand); in MSP430TargetLowering()
|