| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 40 UXTB, enumerator
60 case AArch64_AM::UXTB: return "uxtb"; in getShiftExtendName()
127 case 0: return AArch64_AM::UXTB; in getExtendType()
154 case AArch64_AM::UXTB: return 0; break; in getExtendEncoding()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 40 UXTB, enumerator
60 case AArch64_AM::UXTB: return "uxtb"; in getShiftExtendName()
127 case 0: return AArch64_AM::UXTB; in getExtendType()
154 case AArch64_AM::UXTB: return 0; break; in getExtendEncoding()
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-operand-rn-t32.json | 59 "Uxtb", // UXTB{<c>}{<q>} {<Rd>}, <Rm> ; T1
60 // UXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
|
| D | cond-rd-operand-rn-ror-amount-a32.json | 35 "Uxtb", // UXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
|
| D | cond-rd-operand-rn-ror-amount-t32.json | 35 "Uxtb", // UXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
|
| D | cond-rd-operand-rn-a32.json | 49 "Uxtb", // UXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
|
| /external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/ |
| D | uxtb.ll | 1 ; Test the UXTB and UXTH instructions.
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 512 # UXTB/UXTH
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 521 # UXTB/UXTH
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 521 # UXTB/UXTH
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 359 UXTB, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 400 UXTB, enumerator
|
| /external/vixl/test/aarch64/ |
| D | test-api-aarch64.cc | 355 VIXL_CHECK(!Operand(w11, UXTB).IsPlainRegister()); in TEST()
|
| D | test-disasm-aarch64.cc | 198 COMPARE_MACRO(Mov(w10, Operand(w11, UXTB)), "uxtb w10, w11"); in TEST()
199 COMPARE_MACRO(Mov(x12, Operand(x13, UXTB, 1)), "ubfiz x12, x13, #1, #8"); in TEST()
432 COMPARE(add(w0, w1, Operand(w2, UXTB)), "add w0, w1, w2, uxtb"); in TEST()
433 COMPARE(adds(x3, x4, Operand(w5, UXTB, 1)), "adds x3, x4, w5, uxtb #1"); in TEST()
442 COMPARE(cmn(w0, Operand(w1, UXTB, 2)), "cmn w0, w1, uxtb #2"); in TEST()
445 COMPARE(add(w0, wsp, Operand(w1, UXTB)), "add w0, wsp, w1, uxtb"); in TEST()
458 COMPARE(sub(w0, w1, Operand(w2, UXTB)), "sub w0, w1, w2, uxtb"); in TEST()
459 COMPARE(subs(x3, x4, Operand(w5, UXTB, 1)), "subs x3, x4, w5, uxtb #1"); in TEST()
471 COMPARE(sub(w0, wsp, Operand(w1, UXTB)), "sub w0, wsp, w1, uxtb"); in TEST()
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| D | test-assembler-aarch64.cc | 491 __ Mvn(w10, Operand(w2, UXTB)); in TEST()
666 __ Mov(w23, Operand(w13, UXTB)); in TEST()
720 __ Mov(w19, Operand(w11, UXTB, 1)); in TEST()
801 __ Orr(w6, w0, Operand(w1, UXTB)); in TEST()
895 __ Orn(w6, w0, Operand(w1, UXTB)); in TEST()
962 __ And(w6, w0, Operand(w1, UXTB)); in TEST()
1100 __ Bic(w6, w0, Operand(w1, UXTB)); in TEST()
1224 __ Eor(w6, w0, Operand(w1, UXTB)); in TEST()
1291 __ Eon(w6, w0, Operand(w1, UXTB)); in TEST()
8656 __ Add(x10, x0, Operand(x1, UXTB, 0)); in TEST()
[all …]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 605 @ UXTB/UXTH
|
| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 123 return Operand(InputRegister32(index), UXTB); in InputOperand2_32()
153 return Operand(InputRegister64(index), UXTB); in InputOperand2_64()
1636 ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(ldaxrb, stlxrb, UXTB, in AssembleArchInstruction()
1642 ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(ldaxrb, stlxrb, UXTB, in AssembleArchInstruction()
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 656 @ UXTB/UXTH
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 656 @ UXTB/UXTH
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 242 return Size == 8 ? ARM::UXTB : ARM::UXTH; in selectSimpleExtOpc()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ExpandPseudoInsts.cpp | 908 AArch64_AM::getArithExtendImm(AArch64_AM::UXTB, 0), in expandMI()
|
| D | AArch64SchedCyclone.td | 162 // EXAMPLE: ADDXre Xn, Xm, UXTB #1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ExpandPseudoInsts.cpp | 938 AArch64_AM::getArithExtendImm(AArch64_AM::UXTB, 0), in expandMI()
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_T2_32.c | 180 #define UXTB 0xb2c0 macro
753 return push_inst16(compiler, UXTB | RD3(dst) | RN3(arg2)); in emit_op_imm()
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| D | sljitNativeARM_32.c | 133 #define UXTB 0xe6ef0070 macro
1050 return push_inst(compiler, (op == SLJIT_MOV_U8 ? UXTB : SXTB) | RD(dst) | RM(src2)); in emit_single_op()
|