| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 41 UXTH, enumerator
61 case AArch64_AM::UXTH: return "uxth"; in getShiftExtendName()
128 case 1: return AArch64_AM::UXTH; in getExtendType()
155 case AArch64_AM::UXTH: return 1; break; in getExtendEncoding()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | misched-int-basic.mir | 41 # CHECK: SU(4): %4:gprnopc = UXTH %3:gprnopc, 0, 14, $noreg
116 %4 = UXTH %3, 0, 14, $noreg
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 41 UXTH, enumerator
61 case AArch64_AM::UXTH: return "uxth"; in getShiftExtendName()
128 case 1: return AArch64_AM::UXTH; in getExtendType()
155 case AArch64_AM::UXTH: return 1; break; in getExtendEncoding()
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-operand-rn-t32.json | 62 "Uxth" // UXTH{<c>}{<q>} {<Rd>}, <Rm> ; T1
63 // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
|
| D | cond-rd-operand-rn-ror-amount-a32.json | 37 "Uxth" // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
|
| D | cond-rd-operand-rn-ror-amount-t32.json | 37 "Uxth" // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
|
| D | cond-rd-operand-rn-a32.json | 51 "Uxth" // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
|
| /external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/ |
| D | uxtb.ll | 1 ; Test the UXTB and UXTH instructions.
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 512 # UXTB/UXTH
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 521 # UXTB/UXTH
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 521 # UXTB/UXTH
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 360 UXTH, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 401 UXTH, enumerator
|
| /external/vixl/test/aarch64/ |
| D | test-api-aarch64.cc | 357 VIXL_CHECK(!Operand(w13, UXTH).IsPlainRegister()); in TEST()
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 605 @ UXTB/UXTH
|
| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 125 return Operand(InputRegister32(index), UXTH); in InputOperand2_32()
155 return Operand(InputRegister64(index), UXTH); in InputOperand2_64()
1646 ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(ldaxrh, stlxrh, UXTH, in AssembleArchInstruction()
1652 ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(ldaxrh, stlxrh, UXTH, in AssembleArchInstruction()
|
| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_post_twiddle_overlap.s | 133 UXTH R5, R10, ROR #16
134 UXTH R10, R10
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 656 @ UXTB/UXTH
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 656 @ UXTB/UXTH
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 242 return Size == 8 ? ARM::UXTB : ARM::UXTH; in selectSimpleExtOpc()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ExpandPseudoInsts.cpp | 913 AArch64_AM::getArithExtendImm(AArch64_AM::UXTH, 0), in expandMI()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ExpandPseudoInsts.cpp | 943 AArch64_AM::getArithExtendImm(AArch64_AM::UXTH, 0), in expandMI()
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_T2_32.c | 182 #define UXTH 0xb280 macro
763 return push_inst16(compiler, UXTH | RD3(dst) | RN3(arg2)); in emit_op_imm()
|
| D | sljitNativeARM_32.c | 134 #define UXTH 0xe6ff0070 macro
1067 return push_inst(compiler, (op == SLJIT_MOV_U16 ? UXTH : SXTH) | RD(dst) | RM(src2)); in emit_single_op()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2644 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } } in ARMEmitIntExt()
2884 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
|