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Searched refs:UXTW (Results 1 – 25 of 36) sorted by relevance

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/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AddressingModes.h42 UXTW, enumerator
62 case AArch64_AM::UXTW: return "uxtw"; in getShiftExtendName()
129 case 2: return AArch64_AM::UXTW; in getExtendType()
156 case AArch64_AM::UXTW: return 2; break; in getExtendEncoding()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AddressingModes.h42 UXTW, enumerator
62 case AArch64_AM::UXTW: return "uxtw"; in getShiftExtendName()
129 case 2: return AArch64_AM::UXTW; in getExtendType()
156 case AArch64_AM::UXTW: return 2; break; in getExtendEncoding()
/external/vixl/src/aarch64/
Doperands-aarch64.cc368 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_); in ToExtendedRegister()
407 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); in MemOperand()
468 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); in MemOperand()
Ddisasm-aarch64.cc5609 (((instr->GetExtendMode() == UXTW) && (instr->GetSixtyFourBits() == 0)) || in SubstituteExtendField()
5639 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; in SubstituteLSRegOffsetField()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td1057 // UXTW(8|16|32|64)
1058 def ZPR#RegWidth#AsmOpndExtUXTW8Only : ZPRExtendAsmOperand<"UXTW", RegWidth, 8, 0b1>;
1059 def ZPR#RegWidth#AsmOpndExtUXTW8 : ZPRExtendAsmOperand<"UXTW", RegWidth, 8>;
1060 def ZPR#RegWidth#AsmOpndExtUXTW16 : ZPRExtendAsmOperand<"UXTW", RegWidth, 16>;
1061 def ZPR#RegWidth#AsmOpndExtUXTW32 : ZPRExtendAsmOperand<"UXTW", RegWidth, 32>;
1062 def ZPR#RegWidth#AsmOpndExtUXTW64 : ZPRExtendAsmOperand<"UXTW", RegWidth, 64>;
1064 …def ZPR#RegWidth#ExtUXTW8Only : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8, "On…
1065 def ZPR#RegWidth#ExtUXTW8 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8>;
1066 def ZPR#RegWidth#ExtUXTW16 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 16>;
1067 def ZPR#RegWidth#ExtUXTW32 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 32>;
[all …]
DAArch64FastISel.cpp717 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
741 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
801 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
838 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
860 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
1037 Addr.getExtendType() == AArch64_AM::UXTW ) in simplifyAddress()
1048 if (Addr.getExtendType() == AArch64_AM::UXTW) in simplifyAddress()
1824 if (Addr.getExtendType() == AArch64_AM::UXTW || in emitLoad()
2113 if (Addr.getExtendType() == AArch64_AM::UXTW || in emitStore()
DAArch64ISelDAGToDAG.cpp443 return AArch64_AM::UXTW; in getExtendTypeForNode()
461 return AArch64_AM::UXTW; in getExtendTypeForNode()
641 if (Ext == AArch64_AM::UXTW && in SelectArithExtendedRegister()
/external/vixl/test/aarch64/
Dtest-disasm-aarch64.cc435 COMPARE(adds(x9, x10, Operand(x11, UXTW, 3)), "adds x9, x10, w11, uxtw #3"); in TEST()
447 COMPARE(add(wsp, wsp, Operand(w4, UXTW, 2)), "add wsp, wsp, w4, lsl #2"); in TEST()
461 COMPARE(subs(x9, x10, Operand(x11, UXTW, 3)), "subs x9, x10, w11, uxtw #3"); in TEST()
473 COMPARE(sub(wsp, wsp, Operand(w4, UXTW, 2)), "sub wsp, wsp, w4, lsl #2"); in TEST()
1106 COMPARE(ldr(w0, MemOperand(x1, w2, UXTW)), "ldr w0, [x1, w2, uxtw]"); in TEST()
1107 COMPARE(ldr(w3, MemOperand(x4, w5, UXTW, 2)), "ldr w3, [x4, w5, uxtw #2]"); in TEST()
1116 COMPARE(ldr(x0, MemOperand(x1, w2, UXTW)), "ldr x0, [x1, w2, uxtw]"); in TEST()
1117 COMPARE(ldr(x3, MemOperand(x4, w5, UXTW, 3)), "ldr x3, [x4, w5, uxtw #3]"); in TEST()
1127 COMPARE(str(w0, MemOperand(x1, w2, UXTW)), "str w0, [x1, w2, uxtw]"); in TEST()
1128 COMPARE(str(w3, MemOperand(x4, w5, UXTW, 2)), "str w3, [x4, w5, uxtw #2]"); in TEST()
[all …]
Dtest-simulator-aarch64.cc294 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, n_index_shift)); in Test1Op_Helper()
441 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); in Test2Op_Helper()
445 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); in Test2Op_Helper()
586 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); in Test3Op_Helper()
590 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); in Test3Op_Helper()
594 __ Ldr(fa, MemOperand(inputs_base, index_a, UXTW, index_shift)); in Test3Op_Helper()
736 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); in TestCmp_Helper()
740 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); in TestCmp_Helper()
876 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); in TestCmpZero_Helper()
1020 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, n_index_shift)); in TestFPToFixed_Helper()
[all …]
Dtest-api-aarch64.cc361 VIXL_CHECK(!Operand(w15, UXTW).IsPlainRegister()); in TEST()
Dtest-cpu-features-aarch64.cc177 TEST_NONE(add_0, add(w0, w1, Operand(w2, UXTW, 3)))
304 TEST_NONE(ldrh_3, ldrh(w0, MemOperand(x1, w2, UXTW, 1)))
313 TEST_NONE(ldrsb_7, ldrsb(w0, MemOperand(x1, w2, UXTW, 0)))
324 TEST_NONE(ldrsh_6, ldrsh(w0, MemOperand(x1, w2, UXTW, 0)))
344 TEST_NONE(ldr_10, ldr(x0, MemOperand(x1, w2, UXTW, 3)))
460 TEST_NONE(strh_3, strh(w0, MemOperand(x1, w2, UXTW, 0)))
470 TEST_NONE(str_8, str(x0, MemOperand(x1, w2, UXTW, 0)))
674 TEST_FP(ldr_13, ldr(h0, MemOperand(x1, w2, UXTW, 1)))
708 TEST_FP(str_11, str(h0, MemOperand(x1, w2, UXTW, 1)))
710 TEST_FP(str_13, str(s0, MemOperand(x1, w2, UXTW, 0)))
[all …]
Dtest-assembler-aarch64.cc495 __ Mvn(x14, Operand(w2, UXTW, 4)); in TEST()
670 __ Mov(x27, Operand(w13, UXTW, 4)); in TEST()
731 __ Mov(x29, Operand(x12, UXTW, 1)); in TEST()
803 __ Orr(w8, w0, Operand(w1, UXTW, 2)); in TEST()
897 __ Orn(w8, w0, Operand(w1, UXTW, 2)); in TEST()
964 __ And(w8, w0, Operand(w1, UXTW, 2)); in TEST()
1102 __ Bic(w8, w0, Operand(w1, UXTW, 2)); in TEST()
1226 __ Eor(w8, w0, Operand(w1, UXTW, 2)); in TEST()
1293 __ Eon(w8, w0, Operand(w1, UXTW, 2)); in TEST()
3675 __ Ldr(h3, MemOperand(x17, x18, UXTW, 1)); in TEST()
[all …]
/external/v8/src/regexp/arm64/
Dregexp-macro-assembler-arm64.cc184 __ Add(x10, code_pointer(), Operand(w10, UXTW)); in Backtrack()
574 __ Ldrb(w11, MemOperand(x11, w10, UXTW)); in CheckBitInTable()
655 __ Ldrb(w10, MemOperand(x10, current_character(), UXTW)); in CheckSpecialCharacterClass()
668 __ Ldrb(w10, MemOperand(x10, current_character(), UXTW)); in CheckSpecialCharacterClass()
/external/v8/src/arm64/
Dassembler-arm64-inl.h337 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
429 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
479 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
Ddisasm-arm64.cc3943 (((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) || in SubstituteExtendField()
3967 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; in SubstituteLSRegOffsetField()
Dconstants-arm64.h377 UXTW = 2, enumerator
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h361 UXTW, enumerator
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp670 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
694 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
754 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
791 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
813 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
991 Addr.getExtendType() == AArch64_AM::UXTW ) in simplifyAddress()
1002 if (Addr.getExtendType() == AArch64_AM::UXTW) in simplifyAddress()
1770 if (Addr.getExtendType() == AArch64_AM::UXTW || in emitLoad()
2037 if (Addr.getExtendType() == AArch64_AM::UXTW || in emitStore()
/external/v8/src/wasm/baseline/arm64/
Dliftoff-assembler-arm64.h107 if (offset_imm == 0) return MemOperand(addr.X(), offset.W(), UXTW); in GetMemOp()
110 return MemOperand(addr.X(), tmp, UXTW); in GetMemOp()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h402 UXTW, enumerator
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp1104 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1110 ExtType == AArch64_AM::UXTW) ) { in printArithExtend()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp962 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
968 ExtType == AArch64_AM::UXTW) ) { in printArithExtend()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp1086 if (!MatchShift && (ShiftExtendTy == AArch64_AM::UXTW || in isSVEDataVectorRegWithShiftExtend()
1238 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW || in isExtend()
1274 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) && in isMemWExtend()
1715 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTW; in addExtendOperands()
2668 .Case("uxtw", AArch64_AM::UXTW) in tryParseOptionalShiftExtend()
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp990 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW || in isExtend()
1025 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) && in isMemWExtend()
1561 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTW; in addExtendOperands()
2391 .Case("uxtw", AArch64_AM::UXTW) in tryParseOptionalShiftExtend()
/external/v8/src/compiler/arm64/
Dcode-generator-arm64.cc1657 ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(ldaxr, stlxr, UXTW, Register32); in AssembleArchInstruction()
2335 __ Add(temp, temp, Operand(input, UXTW, 2)); in AssembleArchTableSwitch()

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