| /external/libxaac/decoder/armv8/ |
| D | ixheaacd_overlap_add2.s | 82 LD2 {V10.4H, V11.4H}, [X3], #16
96 UMULL V19.4S, V8.4H, V10.4H
106 SMLAL V19.4S, V9.4H, V10.4H
117 LD2 {V10.4H, V11.4H}, [X3], #16
143 UMULL V19.4S, V8.4H, V10.4H
149 SMLAL V19.4S, V9.4H, V10.4H
213 LD2 {V10.4H, V11.4H}, [X11], X12
222 REV64 V10.4H, V10.4H
246 UMLSL V19.4S, V12.4H, V10.4H
257 SMLSL V19.4S, V13.4H, V10.4H
[all …]
|
| D | ixheaacd_sbr_imdct_using_fft.s | 173 LD2 {V10.S, V11.S}[0], [X5] , X1
184 LD2 {V10.S, V11.S}[1], [X6] , X1
193 LD2 {V10.S, V11.S}[2], [X7] , X1
202 LD2 {V10.S, V11.S}[3], [X11] , X1
224 ADD V15.4S, V10.4S, V1.4S
225 SUB V13.4S, V10.4S, V1.4S
226 ADD V10.4S, V11.4S, V2.4S
231 ADD V17.4S, V14.4S, V10.4S
232 SUB V15.4S, V14.4S, V10.4S
235 SUB V10.4S, V16.4S, V12.4S
[all …]
|
| D | ixheaacd_overlap_add1.s | 65 DUP V10.4S, W7
108 SQADD V14.4S, V14.4S, V10.4S
127 SQADD V8.4S, V8.4S, V10.4S
190 SQADD V14.4S, V14.4S, V10.4S
195 SQADD V8.4S, V8.4S, V10.4S
244 SQADD V14.4S, V14.4S, V10.4S
256 SQADD V8.4S, V8.4S, V10.4S
306 SQADD V14.4S, V14.4S, V10.4S
307 SQADD V8.4S, V8.4S, V10.4S
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/autohvx/ |
| D | isel-expand-unaligned-loads.ll | 14 ; CHECK-DAG: v[[V10:[0-9]+]] = vmem(r[[B01:[0-9]+]]+#0)
18 ; CHECK-DAG: valign(v[[V11]],v[[V10]],r[[B01]])
|
| D | bswap.ll | 23 ; CHECK: [[V10:v[0-9]+]] = vsplat([[R10]])
24 ; CHECK: v0 = vdelta(v0,[[V10]])
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCallingConv.td | 87 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
101 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
|
| D | HexagonRegisterInfo.cpp | 70 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, in getCallerSavedRegs()
|
| /external/libchrome/mojo/public/interfaces/bindings/tests/ |
| D | test_structs.mojom | 208 const int32 V10 = -2147483648;
233 int32 f10 = V10;
264 const uint64 V10 = 1234567890123456;
280 uint64 f10 = V10;
|
| /external/opencensus-java/api/src/test/java/io/opencensus/stats/ |
| D | ViewDataTest.java | 223 createView(DISTRIBUTION), ImmutableMap.of(Arrays.asList(V10, V20), CountData.create(100))); in preventAggregationAndAggregationDataMismatch_Distribution_Count()
274 private static final TagValue V10 = TagValue.create("v10"); field in ViewDataTest
289 Arrays.asList(V10, V20),
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | smlad11.ll | 9 ; CHECK: [[V10:%[0-9]+]] = bitcast i16* %arrayidx to i32*
10 ; CHECK: [[V11:%[0-9]+]] = load i32, i32* [[V10]], align 2
|
| D | smlad0.ll | 68 ; CHECK: %mac1{{\.}}058 = phi i32 [ [[V10:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ]
70 ; CHECK: [[V10]] = call i32 @llvm.arm.smlad(i32 %{{.*}}, i32 %{{.*}}, i32 %mac1{{\.}}058)
|
| /external/sonivox/arm-wt-22k/vectors/ |
| D | abba.imy | 8 VOLUME:V10
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 51 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,V11,V12,V13]>>
109 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>,
|
| D | PPCRegisterInfo.td | 180 def V10 : VR<10, "v10">, DwarfRegNum<[87, 87]>;
299 (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCBaseInfo.h | 41 case R10: case X10: case F10: case V10: case CR2EQ: return 10; in getPPCRegisterNumbering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/X86/ |
| D | x86-vec_demanded_elts.ll | 32 ; CHECK-NEXT: [[V10:%.*]] = insertelement <4 x float> undef, float %f, i32 0
33 ; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.x86.sse.cvtss2si64(<4 x float> [[V10]])
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 70 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, in getCallerSavedRegs()
|
| D | HexagonRegisterInfo.td | 188 def W5 : Rd<10, "v11:10", [V10, V11]>, DwarfRegNum<[109]>;
274 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11,
|
| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| D | SystemZMCTargetDesc.cpp | 104 SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11,
|
| /external/clang/test/Parser/ |
| D | MicrosoftExtensions.cpp | 320 …__declspec(property(get=GetV,)) int V10; // expected-error {{expected 'get' or 'put' in property d…
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| D | SystemZMCTargetDesc.cpp | 104 SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 106 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
126 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 245 V8, V9, V10, V11, V12, V13]>>>,
250 V8, V9, V10, V11, V12, V13]>>>,
|
| /external/llvm/test/Transforms/SLPVectorizer/X86/ |
| D | insert-element-build-vector.ll | 319 ; CHECK-DAG: %[[V10:.+]] = extractelement <2 x double> %[[V9]], i32 0
320 ; CHECK-DAG: %[[I3:.+]] = insertelement <4 x double> %i2, double %[[V10]], i32 1
|
| /external/boringssl/src/ssl/test/runner/poly1305/ |
| D | sum_s390x.s | 26 #define R_1 V10
|