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/external/libxaac/decoder/armv8/
Dixheaacd_overlap_add2.s82 LD2 {V10.4H, V11.4H}, [X3], #16
98 UMLSL V19.4S, V12.4H, V11.4H
113 SMLSL V19.4S, V13.4H, V11.4H
117 LD2 {V10.4H, V11.4H}, [X3], #16
144 UMLSL V19.4S, V12.4H, V11.4H
150 SMLSL V19.4S, V13.4H, V11.4H
213 LD2 {V10.4H, V11.4H}, [X11], X12
223 REV64 V11.4H, V11.4H
234 UMULL V19.4S, V9.4H, V11.4H
254 SMLAL V19.4S, V8.4H, V11.4H
[all …]
Dixheaacd_sbr_imdct_using_fft.s173 LD2 {V10.S, V11.S}[0], [X5] , X1
184 LD2 {V10.S, V11.S}[1], [X6] , X1
193 LD2 {V10.S, V11.S}[2], [X7] , X1
202 LD2 {V10.S, V11.S}[3], [X11] , X1
226 ADD V10.4S, V11.4S, V2.4S
227 SUB V1.4S, V11.4S, V2.4S
229 ADD V11.4S, V17.4S, V15.4S
249 ADD V16.4S, V4.4S, V11.4S
253 SUB V10.4S, V4.4S, V11.4S
261 SUB V11.4S, V8.4S, V17.4S
[all …]
Dixheaacd_overlap_add1.s59 DUP V11.8H, W4
100 SQSHL V15.4S, V15.4S, V11.4S
117 SQSHL V12.4S, V12.4S, V11.4S
165 SQSHL V15.4S, V15.4S, V11.4S
167 SQSHL V12.4S, V12.4S, V11.4S
221 SQSHL V15.4S, V15.4S, V11.4S
223 SQSHL V12.4S, V12.4S, V11.4S
287 SQSHL V15.4S, V15.4S, V11.4S
289 SQSHL V12.4S, V12.4S, V11.4S
/external/clang/test/Parser/
DMicrosoftExtensions.cpp321 __declspec(property(get=GetV,put=SetV)) int V11; // no-warning
332 int i = sp.V11;
333 sp.V11 = i++;
334 sp.V11 += 8;
335 sp.V11++;
336 ++sp.V11;
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/autohvx/
Disel-expand-unaligned-loads.ll15 ; CHECK-DAG: v[[V11:[0-9]+]] = vmem(r[[B01]]+#1)
18 ; CHECK-DAG: valign(v[[V11]],v[[V10]],r[[B01]])
19 ; CHECK-DAG: valign(v[[V12]],v[[V11]],r[[B01]])
Dbswap.ll32 ; CHECK: [[V11:v[0-9]+]] = vsplat([[R11]])
33 ; CHECK: v0 = vdelta(v0,[[V11]])
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td87 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
101 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
DHexagonRegisterInfo.cpp70 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, in getCallerSavedRegs()
/external/libchrome/mojo/public/interfaces/bindings/tests/
Dtest_structs.mojom209 const int32 V11 = -1;
234 int32 f11 = V11;
265 const uint64 V11 = 9007199254740991; // Number.MAX_SAFE_INTEGER
281 uint64 f11 = V11;
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dsmlad11.ll10 ; CHECK: [[V11:%[0-9]+]] = load i32, i32* [[V10]], align 2
11 ; CHECK: [[V12:%[0-9]+]] = call i32 @llvm.arm.smlad(i32 [[V9]], i32 [[V11]], i32 %mac1{{\.}}054)
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCCallingConv.td51 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,V11,V12,V13]>>
109 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>,
DPPCRegisterInfo.td181 def V11 : VR<11, "v11">, DwarfRegNum<[88, 88]>;
299 (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
DPPCInstr64Bit.td71 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
97 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/
DPPCBaseInfo.h42 case R11: case X11: case F11: case V11: case CR2UN: return 11; in getPPCRegisterNumbering()
/external/llvm/test/Instrumentation/SanitizerCoverage/
Dcoverage.ll87 ; CHECK-8BIT: [[V11:%[0-9]*]] = load i8{{.*}}!nosanitize
88 ; CHECK-8BIT: [[V12:%[0-9]*]] = add i8 [[V11]], 1
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp70 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, in getCallerSavedRegs()
DHexagonRegisterInfo.td188 def W5 : Rd<10, "v11:10", [V10, V11]>, DwarfRegNum<[109]>;
274 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11,
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCTargetDesc.cpp104 SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCTargetDesc.cpp104 SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp106 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
126 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCCallingConv.td245 V8, V9, V10, V11, V12, V13]>>>,
250 V8, V9, V10, V11, V12, V13]>>>,
/external/llvm/test/Transforms/SLPVectorizer/X86/
Dinsert-element-build-vector.ll321 ; CHECK-DAG: %[[V11:.+]] = extractelement <2 x double> %[[V9]], i32 1
322 ; CHECK-DAG: %[[I4:.+]] = insertelement <4 x double> %i3, double %[[V11]], i32 0
/external/boringssl/src/ssl/test/runner/poly1305/
Dsum_s390x.s27 #define R_2 V11
/external/llvm/lib/Target/PowerPC/
DPPCCallingConv.td192 V8, V9, V10, V11, V12, V13]>>>,
/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp95 PPC::V8, PPC::V9, PPC::V10, PPC::V11,

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