Searched refs:VALU (Results 1 – 25 of 40) sorted by relevance
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 29 field bit VALU = 0;
38 // VALU instruction formats.
126 let TSFlags{1} = VALU;
191 …let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)…
207 let VALU = 1;
322 let VALU = 1;
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| D | SISchedule.td | 44 // FIXME: Should there be a class for instructions which are VALU
45 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
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| D | GCNHazardRecognizer.h | 71 int checkVALUHazards(MachineInstr *VALU);
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| D | VOPInstructions.td | 37 let VALU = 1;
117 let VALU = 1;
419 let VALU = 1;
517 let VALU = 1;
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| D | GCNHazardRecognizer.cpp | 559 int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) { in checkVALUHazards() argument
568 for (const MachineOperand &Def : VALU->defs()) { in checkVALUHazards()
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| D | SIDefines.h | 23 VALU = 1 << 1, enumerator
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| D | SIInstrInfo.h | 309 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
313 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
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| D | VOP1Instructions.td | 54 let VALU = 1;
156 let VALU = 1;
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | split-smrd.ll | 5 ; the VALU, we are also moving its users to the VALU.
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| D | sgpr-control-flow.ll | 63 ; VALU for i1 phi.
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| D | uniform-cfg.ll | 121 ; be selected for the SALU and then later moved to the VALU.
146 ; be selected for the SALU and then later moved to the VALU.
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| D | valu-i1.ll | 7 ; moved using VALU instructions
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| D | salu-to-valu.ll | 53 ; Test moving an SMRD instruction to the VALU
90 ; Test moving an SMRD with an immediate offset to the VALU
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| D | and.ll | 60 ; can fold into the s_and_b32 and the VALU one is materialized
72 ; Just to stop future replacement of copy to vgpr + store with VALU op.
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | split-smrd.ll | 5 ; the VALU, we are also moving its users to the VALU.
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| D | sgpr-control-flow.ll | 104 ; VALU for i1 phi.
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| D | uniform-cfg.ll | 119 ; be selected for the SALU and then later moved to the VALU.
144 ; be selected for the SALU and then later moved to the VALU.
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| D | break-smem-soft-clauses.mir | 275 # Regular VALU instruction breaks clause, no nop needed
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| D | salu-to-valu.ll | 53 ; Test moving an SMRD instruction to the VALU
90 ; Test moving an SMRD with an immediate offset to the VALU
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| D | and.ll | 61 ; can fold into the s_and_b32 and the VALU one is materialized
73 ; Just to stop future replacement of copy to vgpr + store with VALU op.
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| D | valu-i1.ll | 7 ; moved using VALU instructions
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SISchedule.td | 44 // FIXME: Should there be a class for instructions which are VALU
45 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
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| D | SIInstrFormats.td | 23 field bits<1> VALU = 0;
59 let TSFlags{4} = VALU;
121 let VALU = 1;
158 let VALU = 1;
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| D | SIDefines.h | 20 VALU = 1 << 4, enumerator
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| D | SIInstrInfo.h | 192 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
196 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
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