1 //===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines hazard recognizers for scheduling on GCN processors. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H 15 #define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H 16 17 #include "llvm/ADT/BitVector.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/CodeGen/ScheduleHazardRecognizer.h" 20 #include <list> 21 22 namespace llvm { 23 24 class MachineFunction; 25 class MachineInstr; 26 class MachineOperand; 27 class MachineRegisterInfo; 28 class ScheduleDAG; 29 class SIInstrInfo; 30 class SIRegisterInfo; 31 class GCNSubtarget; 32 33 class GCNHazardRecognizer final : public ScheduleHazardRecognizer { 34 // This variable stores the instruction that has been emitted this cycle. It 35 // will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is 36 // called. 37 MachineInstr *CurrCycleInstr; 38 std::list<MachineInstr*> EmittedInstrs; 39 const MachineFunction &MF; 40 const GCNSubtarget &ST; 41 const SIInstrInfo &TII; 42 const SIRegisterInfo &TRI; 43 44 /// RegUnits of uses in the current soft memory clause. 45 BitVector ClauseUses; 46 47 /// RegUnits of defs in the current soft memory clause. 48 BitVector ClauseDefs; 49 resetClause()50 void resetClause() { 51 ClauseUses.reset(); 52 ClauseDefs.reset(); 53 } 54 55 void addClauseInst(const MachineInstr &MI); 56 57 int getWaitStatesSince(function_ref<bool(MachineInstr *)> IsHazard); 58 int getWaitStatesSinceDef(unsigned Reg, 59 function_ref<bool(MachineInstr *)> IsHazardDef = 60 [](MachineInstr *) { return true; }); 61 int getWaitStatesSinceSetReg(function_ref<bool(MachineInstr *)> IsHazard); 62 63 int checkSoftClauseHazards(MachineInstr *SMEM); 64 int checkSMRDHazards(MachineInstr *SMRD); 65 int checkVMEMHazards(MachineInstr* VMEM); 66 int checkDPPHazards(MachineInstr *DPP); 67 int checkDivFMasHazards(MachineInstr *DivFMas); 68 int checkGetRegHazards(MachineInstr *GetRegInstr); 69 int checkSetRegHazards(MachineInstr *SetRegInstr); 70 int createsVALUHazard(const MachineInstr &MI); 71 int checkVALUHazards(MachineInstr *VALU); 72 int checkVALUHazardsHelper(const MachineOperand &Def, const MachineRegisterInfo &MRI); 73 int checkRWLaneHazards(MachineInstr *RWLane); 74 int checkRFEHazards(MachineInstr *RFE); 75 int checkInlineAsmHazards(MachineInstr *IA); 76 int checkAnyInstHazards(MachineInstr *MI); 77 int checkReadM0Hazards(MachineInstr *SMovRel); 78 public: 79 GCNHazardRecognizer(const MachineFunction &MF); 80 // We can only issue one instruction per cycle. atIssueLimit()81 bool atIssueLimit() const override { return true; } 82 void EmitInstruction(SUnit *SU) override; 83 void EmitInstruction(MachineInstr *MI) override; 84 HazardType getHazardType(SUnit *SU, int Stalls) override; 85 void EmitNoop() override; 86 unsigned PreEmitNoops(SUnit *SU) override; 87 unsigned PreEmitNoops(MachineInstr *) override; 88 void AdvanceCycle() override; 89 void RecedeCycle() override; 90 }; 91 92 } // end namespace llvm 93 94 #endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H 95