| /external/arm-neon-tests/ |
| D | ref-rvct-neon-nofp16.txt | 4261 VEOR/VEORQ output:
4262 VEOR/VEORQ:0:result_int8x8 [] = { fffffff2, fffffff3, fffffff0, fffffff1, fffffff6, fffffff7, fffff…
4263 VEOR/VEORQ:1:result_int16x4 [] = { c, d, e, f, }
4264 VEOR/VEORQ:2:result_int32x2 [] = { fffffff3, fffffff2, }
4265 VEOR/VEORQ:3:result_int64x1 [] = { ffffffffffffff94, }
4266 VEOR/VEORQ:4:result_uint8x8 [] = { e4, e5, e6, e7, e0, e1, e2, e3, }
4267 VEOR/VEORQ:5:result_uint16x4 [] = { ffee, ffef, ffec, ffed, }
4268 VEOR/VEORQ:6:result_uint32x2 [] = { ffffffd8, ffffffd9, }
4269 VEOR/VEORQ:7:result_uint64x1 [] = { fffffffffffffff2, }
4270 VEOR/VEORQ:8:result_poly8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
[all …]
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| D | ref-rvct-neon.txt | 4797 VEOR/VEORQ output:
4798 VEOR/VEORQ:0:result_int8x8 [] = { fffffff2, fffffff3, fffffff0, fffffff1, fffffff6, fffffff7, fffff…
4799 VEOR/VEORQ:1:result_int16x4 [] = { c, d, e, f, }
4800 VEOR/VEORQ:2:result_int32x2 [] = { fffffff3, fffffff2, }
4801 VEOR/VEORQ:3:result_int64x1 [] = { ffffffffffffff94, }
4802 VEOR/VEORQ:4:result_uint8x8 [] = { e4, e5, e6, e7, e0, e1, e2, e3, }
4803 VEOR/VEORQ:5:result_uint16x4 [] = { ffee, ffef, ffec, ffed, }
4804 VEOR/VEORQ:6:result_uint32x2 [] = { ffffffd8, ffffffd9, }
4805 VEOR/VEORQ:7:result_uint64x1 [] = { fffffffffffffff2, }
4806 VEOR/VEORQ:8:result_poly8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
[all …]
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| D | ref-rvct-all.txt | 4797 VEOR/VEORQ output:
4798 VEOR/VEORQ:0:result_int8x8 [] = { fffffff2, fffffff3, fffffff0, fffffff1, fffffff6, fffffff7, fffff…
4799 VEOR/VEORQ:1:result_int16x4 [] = { c, d, e, f, }
4800 VEOR/VEORQ:2:result_int32x2 [] = { fffffff3, fffffff2, }
4801 VEOR/VEORQ:3:result_int64x1 [] = { ffffffffffffff94, }
4802 VEOR/VEORQ:4:result_uint8x8 [] = { e4, e5, e6, e7, e0, e1, e2, e3, }
4803 VEOR/VEORQ:5:result_uint16x4 [] = { ffee, ffef, ffec, ffed, }
4804 VEOR/VEORQ:6:result_uint32x2 [] = { ffffffd8, ffffffd9, }
4805 VEOR/VEORQ:7:result_uint64x1 [] = { fffffffffffffff2, }
4806 VEOR/VEORQ:8:result_poly8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
[all …]
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| D | expected_input4gcc-nofp16.txt | 4286 VEOR/VEORQ output:
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| D | expected_input4gcc.txt | 4606 VEOR/VEORQ output:
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 785 def : InstRW<[R52WriteFPALU_F3, R52Read_F2, R52Read_F2], (instregex "(VAND|VBIC|VEOR)d")>;
786 def : InstRW<[R52Write2FPALU_F3, R52Read_F2, R52Read_F2], (instregex "(VAND|VBIC|VEOR)q")>;
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| D | ARMScheduleSwift.td | 561 "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
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| D | ARMScheduleA57.td | 1013 (instregex "VAND", "VBIC", "VMVN", "VORR", "VORN", "VEOR")>;
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| D | ARMScheduleA9.td | 2426 // VADD/VAND/VORR/VEOR/VBIC/VORN/VBIT/VBIF/VBSL
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| D | ARMInstrNEON.td | 5127 // VEOR : Vector Bitwise Exclusive OR
7505 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
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| /external/libopus/celt/arm/ |
| D | celt_pitch_xcorr_arm_gnu.s | 187 VEOR q0, q0, q0
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| /external/v8/src/arm/ |
| D | assembler-arm.cc | 4192 enum BinaryBitwiseOp { VAND, VBIC, VBIF, VBIT, VBSL, VEOR, VORR, VORN }; enumerator
4211 case VEOR: in EncodeNeonBinaryBitwiseOp()
4261 emit(EncodeNeonBinaryBitwiseOp(VEOR, NEON_D, dst.code(), src1.code(), in veor()
4270 emit(EncodeNeonBinaryBitwiseOp(VEOR, NEON_Q, dst.code(), src1.code(), in veor()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 544 "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
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| D | ARMScheduleA9.td | 2402 // VADD/VAND/VORR/VEOR/VBIC/VORN/VBIT/VBIF/VBSL
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| D | ARMInstrNEON.td | 4853 // VEOR : Vector Bitwise Exclusive OR
7141 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
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| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 804 def VEOR : LOpInst<"veor", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>;
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 3731 // VEOR : Vector Bitwise Exclusive OR
|