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Searched refs:VLD1DUP (Results 1 – 8 of 8) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelLowering.h237 VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, enumerator
DARMInstrNEON.td1400 // VLD1DUP : Vector Load (single element to all lanes)
1401 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
1413 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8,
1415 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16,
1417 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load,
DARMISelLowering.cpp1368 case ARMISD::VLD1DUP: return "ARMISD::VLD1DUP"; in getTargetNodeName()
11596 case ARMISD::VLD1DUP: NewOpc = ARMISD::VLD1DUP_UPD; NumVecs = 1; break; in CombineBaseUpdate()
11869 SDValue VLDDup = DAG.getMemIntrinsicNode(ARMISD::VLD1DUP, SDLoc(N), SDTys, in PerformVDUPCombine()
12789 case ARMISD::VLD1DUP: in PerformDAGCombine()
DARMISelDAGToDAG.cpp3112 case ARMISD::VLD1DUP: { in Select()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td878 // VLD1DUP : Vector Load (single element to all lanes)
879 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
892 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
893 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
894 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td1359 // VLD1DUP : Vector Load (single element to all lanes)
1360 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
1371 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8,
1373 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16,
1375 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load,
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenAsmWriter.inc8102 // VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32wb_fixed, VLD1DUP...
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc7134 // VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32wb_fixed, VLD1DUP...