| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 192 VLD3DUP, enumerator
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| D | ARMInstrNEON.td | 992 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
993 class VLD3DUP<bits<4> op7_4, string Dt>
1002 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1003 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1004 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1011 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
1012 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
1013 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
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| D | ARMISelLowering.cpp | 923 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; in getTargetNodeName()
7215 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; in CombineBaseUpdate()
7301 NewOpc = ARMISD::VLD3DUP; in CombineVLDDUP()
7956 case ARMISD::VLD3DUP: in PerformDAGCombine()
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| D | ARMISelDAGToDAG.cpp | 2723 case ARMISD::VLD3DUP: { in Select()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 194 VLD3DUP, enumerator
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| D | ARMInstrNEON.td | 1515 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1516 class VLD3DUP<bits<4> op7_4, string Dt>
1525 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1526 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1527 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1534 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1535 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1536 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
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| D | ARMISelLowering.cpp | 1228 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; in getTargetNodeName()
9962 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; in CombineBaseUpdate()
10131 NewOpc = ARMISD::VLD3DUP; in CombineVLDDUP()
11065 case ARMISD::VLD3DUP: in PerformDAGCombine()
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| D | ARMISelDAGToDAG.cpp | 3155 case ARMISD::VLD3DUP: { in Select()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleA57.td | 1345 (instregex "VLD3DUP(d|q)(8|16|32)$",
1346 "VLD3DUP(d|q)(8|16|32)Pseudo$")>;
1349 (instregex "VLD3DUP(d|q)(8|16|32)_UPD")>;
1351 (instregex "VLD3DUP(d|q)(8|16|32)Pseudo_UPD")>;
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| D | ARMISelLowering.h | 239 VLD3DUP, enumerator
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| D | ARMInstrNEON.td | 1564 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1565 class VLD3DUP<bits<4> op7_4, string Dt>
1575 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1576 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1577 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1584 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1585 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1586 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
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| D | ARMISelLowering.cpp | 1370 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; in getTargetNodeName()
11598 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; in CombineBaseUpdate()
11764 NewOpc = ARMISD::VLD3DUP; in CombineVLDDUP()
12791 case ARMISD::VLD3DUP: in PerformDAGCombine()
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| D | ARMISelDAGToDAG.cpp | 3128 case ARMISD::VLD3DUP: { in Select()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmWriter.inc | 8031 // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPqAsm_16, VLD3DUP...
8639 // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP...
8826 // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP...
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| /external/capstone/arch/ARM/ |
| D | ARMGenAsmWriter.inc | 7686 // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP...
7875 // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP...
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