| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 193 VLD4DUP, enumerator
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| D | ARMInstrNEON.td | 1037 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1038 class VLD4DUP<bits<4> op7_4, string Dt>
1048 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1049 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1050 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1057 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
1058 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
1059 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
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| D | ARMISelLowering.cpp | 924 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; in getTargetNodeName()
7216 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; in CombineBaseUpdate()
7304 NewOpc = ARMISD::VLD4DUP; in CombineVLDDUP()
7957 case ARMISD::VLD4DUP: in PerformDAGCombine()
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| D | ARMISelDAGToDAG.cpp | 2729 case ARMISD::VLD4DUP: { in Select()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 195 VLD4DUP, enumerator
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| D | ARMInstrNEON.td | 1560 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1561 class VLD4DUP<bits<4> op7_4, string Dt>
1571 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1572 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1573 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1580 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1581 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1582 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
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| D | ARMISelLowering.cpp | 1229 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; in getTargetNodeName()
9963 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; in CombineBaseUpdate()
10134 NewOpc = ARMISD::VLD4DUP; in CombineVLDDUP()
11066 case ARMISD::VLD4DUP: in PerformDAGCombine()
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| D | ARMISelDAGToDAG.cpp | 3163 case ARMISD::VLD4DUP: { in Select()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleA57.td | 1392 (instregex "VLD4DUP(d|q)(8|16|32)$",
1393 "VLD4DUP(d|q)(8|16|32)Pseudo$")>;
1397 (instregex "VLD4DUP(d|q)(8|16|32)_UPD")>;
1399 (instregex "VLD4DUP(d|q)(8|16|32)Pseudo_UPD")>;
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| D | ARMISelLowering.h | 240 VLD4DUP, enumerator
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| D | ARMInstrNEON.td | 1617 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1618 class VLD4DUP<bits<4> op7_4, string Dt>
1628 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1629 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1630 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1637 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1638 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1639 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
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| D | ARMISelLowering.cpp | 1371 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; in getTargetNodeName()
11599 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; in CombineBaseUpdate()
11767 NewOpc = ARMISD::VLD4DUP; in CombineVLDDUP()
12792 case ARMISD::VLD4DUP: in PerformDAGCombine()
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| D | ARMISelDAGToDAG.cpp | 3136 case ARMISD::VLD4DUP: { in Select()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmWriter.inc | 7133 // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP...
8643 // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP...
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| /external/capstone/arch/ARM/ |
| D | ARMGenAsmWriter.inc | 6207 // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP...
7690 // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP...
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