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Searched refs:VMOVRRD (Results 1 – 25 of 41) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dpeephole-phi.mir14 # CHECK: %1:gpr, %2:gpr = VMOVRRD %0, 14, $noreg
33 %1:gpr, %2:gpr = VMOVRRD %0:dpr, 14, $noreg
Dsingle-issue-r52.mir29 # CHECK: SU(3): %5:gpr, %6:gpr = VMOVRRD %4:dpr, 14, $noreg
81 %5, %6 = VMOVRRD %4, 14, $noreg
Dcortex-a57-misched-vfma.ll71 ; > VMLAfd not-optimized latency to VMOVRRD = 9
148 ; > VMLSfd not-optimized latency to VMOVRRD = 9
Dvector-DAGCombine.ll38 ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
/external/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
DMLxExpansionPass.cpp192 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
DARMISelLowering.h76 VMOVRRD, // double to two gprs. enumerator
DARMISelLowering.cpp1151 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; in getTargetNodeName()
1552 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
2305 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
2327 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
2395 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) { in isUsedByReturnOnly()
3701 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
3703 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
4300 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
4316 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
4487 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST()
[all …]
DARMISelDAGToDAG.cpp442 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
2893 case ARMISD::VMOVRRD: in Select()
2894 ReplaceNode(N, CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32, in Select()
DARMInstrVFP.td1032 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
2290 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
DMLxExpansionPass.cpp192 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
DARMInstructionSelector.cpp222 MIB->setDesc(TII.get(ARM::VMOVRRD)); in selectUnmergeValues()
766 BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::VMOVRRD)) in select()
DARMISelLowering.h103 VMOVRRD, // double to two gprs. enumerator
DARMISelLowering.cpp1277 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; in getTargetNodeName()
1749 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
2529 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
2551 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
2620 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) { in isUsedByReturnOnly()
4228 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
4230 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
4973 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
4989 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
5230 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST()
[all …]
DARMInstrVFP.td26 def arm_fmrrd : SDNode<"ARMISD::VMOVRRD", SDT_VMOVRRD>;
1079 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
2464 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMHazardRecognizer.cpp27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
DMLxExpansionPass.cpp145 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
DARMISelLowering.h79 VMOVRRD, // double to two gprs. enumerator
DARMISelLowering.cpp849 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; in getTargetNodeName()
1195 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
1814 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
1831 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
1866 } else if (Use->getOpcode() == ARMISD::VMOVRRD) { in isUsedByReturnOnly()
3142 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
3158 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
3233 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST()
6958 if (Op0.getOpcode() == ARMISD::VMOVRRD && in PerformVMOVDRRCombine()
7936 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); in PerformDAGCombine()
DARMISelDAGToDAG.cpp358 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
2555 case ARMISD::VMOVRRD: in Select()
2556 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32, in Select()
DARMFastISel.cpp1649 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvector-DAGCombine.ll30 ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
/external/llvm/test/CodeGen/ARM/
Dvector-DAGCombine.ll38 ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/GlobalISel/
Darm-instruction-select.mir288 ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr, [[UNINTERESTING:%[0-9]+]]:gpr = VMOVRRD [[VREG]]
1830 ; CHECK: [[OUT1:%[0-9]+]]:gpr, [[OUT2:%[0-9]+]]:gpr = VMOVRRD %[[DREG]]

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