| /external/llvm/lib/Target/AMDGPU/ |
| D | VIInstrFormats.td | 146 // Encoding used for VOPC instructions encoded as VOP3
147 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
286 // VOPC disallows dst_sel and dst_unused as they have no effect on destination
|
| D | SIInstrFormats.td | 34 field bits<1> VOPC = 0;
70 let TSFlags{13} = VOPC;
127 let VOPC = 1;
429 // Encoding used for VOPC instructions encoded as VOP3
430 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
653 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
|
| D | SIDefines.h | 31 VOPC = 1 << 13, enumerator
|
| D | SIInstrInfo.h | 272 return MI.getDesc().TSFlags & SIInstrFlags::VOPC; in isVOPC()
276 return get(Opcode).TSFlags & SIInstrFlags::VOPC; in isVOPC()
|
| D | SISchedule.td | 45 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
|
| D | SIInstrInfo.td | 1320 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
1329 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1342 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1359 ""); // use $sdst for VOPC
1374 " vcc", // use vcc token as dst for VOPC instructioins
1391 " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
1558 // VOPC instructions are a special case because for the 32-bit
1624 // This class is used only with VOPC instructions. Use $sdst for out operand
2310 def _si : VOPC<op.SI, ins, asm, []>,
2322 def _vi : VOPC<op.VI, ins, asm, []>,
|
| D | SIInstructions.td | 529 // VOPC Instructions
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 41 field bit VOPC = 0;
136 let TSFlags{9} = VOPC;
191 …let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)…
|
| D | VOPCInstructions.td | 32 // VOPC disallows dst_sel and dst_unused as they have no effect on destination
49 // VOPC classes
52 // VOPC instructions are a special case because for the 32-bit
82 let VOPC = 1;
117 // This class is used only with VOPC instructions. Use $sdst for out operand
690 // Encoding used for VOPC instructions encoded as VOP3
691 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
928 // Encoding used for VOPC instructions encoded as VOP3
929 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
|
| D | SIInstrInfo.td | 1100 SDWAVopcDst, // VOPC
1461 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
1479 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1493 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1558 ""); // use $sdst for VOPC
1572 " vcc", // use vcc token as dst for VOPC instructioins
1589 " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
1601 "$sdst", // VOPC
1617 … " $src0_sel $src1_sel", // No dst_sel, dst_unused and output modifiers for VOPC
|
| D | SISchedule.td | 45 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
|
| D | SIDefines.h | 35 VOPC = 1 << 9, enumerator
|
| D | SIInstrInfo.h | 397 return MI.getDesc().TSFlags & SIInstrFlags::VOPC; in isVOPC()
401 return get(Opcode).TSFlags & SIInstrFlags::VOPC; in isVOPC()
|
| D | AMDGPU.td | 218 "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
230 "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
|
| D | VOPInstructions.td | 351 // 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This
|
| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 101 VOP1, VOP2, VOP3, VOPC Instructions
107 VOP1, VOP2, and VOPC instructions based on the operands. If you want to force
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUOperandSyntax.rst | 648 VOP1/VOP2/VOPC SDWA Modifiers
740 VOP1/VOP2/VOPC SDWA Operand Modifiers
|
| D | AMDGPUUsage.rst | 4255 For vector ALU instruction opcodes (VOP1, VOP2, VOP3, VOPC, VOP_DPP, VOP_SDWA),
4259 * _e32 for 32-bit VOP1/VOP2/VOPC
4264 VOP1/VOP2/VOP3/VOPC examples:
|
| D | AMDGPUAsmGFX7.rst | 1055 VOPC chapter
|
| D | AMDGPUAsmGFX8.rst | 1338 VOPC chapter
|
| D | AMDGPUAsmGFX9.rst | 1572 VOPC chapter
|
| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2687 cvtSDWA(Inst, Operands, SIInstrFlags::VOPC); in cvtSdwaVOPC()
2703 if (BasicInstType == SIInstrFlags::VOPC && in cvtSDWA()
2738 case SIInstrFlags::VOPC: { in cvtSDWA()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2280 (SIInstrFlags::VOPC | in validateConstantBusLimitations()
5363 cvtSDWA(Inst, Operands, SIInstrFlags::VOPC, isVI()); in cvtSdwaVOPC()
5390 } else if (BasicInstType == SIInstrFlags::VOPC && in cvtSDWA()
5432 case SIInstrFlags::VOPC: in cvtSDWA()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/ |
| D | sdwa_gfx9.txt | 406 # VOPC
505 # VOPC with arbitrary SGPR destination
|