1//===-- VIInstrFormats.td - VI Instruction Encodings ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// VI Instruction format definitions. 11// 12//===----------------------------------------------------------------------===// 13 14class DSe_vi <bits<8> op> : Enc64 { 15 bits<8> vdst; 16 bits<1> gds; 17 bits<8> addr; 18 bits<8> data0; 19 bits<8> data1; 20 bits<8> offset0; 21 bits<8> offset1; 22 23 let Inst{7-0} = offset0; 24 let Inst{15-8} = offset1; 25 let Inst{16} = gds; 26 let Inst{24-17} = op; 27 let Inst{31-26} = 0x36; //encoding 28 let Inst{39-32} = addr; 29 let Inst{47-40} = data0; 30 let Inst{55-48} = data1; 31 let Inst{63-56} = vdst; 32} 33 34class MUBUFe_vi <bits<7> op> : Enc64 { 35 bits<12> offset; 36 bits<1> offen; 37 bits<1> idxen; 38 bits<1> glc; 39 bits<1> lds; 40 bits<8> vaddr; 41 bits<8> vdata; 42 bits<7> srsrc; 43 bits<1> slc; 44 bits<1> tfe; 45 bits<8> soffset; 46 47 let Inst{11-0} = offset; 48 let Inst{12} = offen; 49 let Inst{13} = idxen; 50 let Inst{14} = glc; 51 let Inst{16} = lds; 52 let Inst{17} = slc; 53 let Inst{24-18} = op; 54 let Inst{31-26} = 0x38; //encoding 55 let Inst{39-32} = vaddr; 56 let Inst{47-40} = vdata; 57 let Inst{52-48} = srsrc{6-2}; 58 let Inst{55} = tfe; 59 let Inst{63-56} = soffset; 60} 61 62class MTBUFe_vi <bits<4> op> : Enc64 { 63 bits<12> offset; 64 bits<1> offen; 65 bits<1> idxen; 66 bits<1> glc; 67 bits<4> dfmt; 68 bits<3> nfmt; 69 bits<8> vaddr; 70 bits<8> vdata; 71 bits<7> srsrc; 72 bits<1> slc; 73 bits<1> tfe; 74 bits<8> soffset; 75 76 let Inst{11-0} = offset; 77 let Inst{12} = offen; 78 let Inst{13} = idxen; 79 let Inst{14} = glc; 80 let Inst{18-15} = op; 81 let Inst{22-19} = dfmt; 82 let Inst{25-23} = nfmt; 83 let Inst{31-26} = 0x3a; //encoding 84 let Inst{39-32} = vaddr; 85 let Inst{47-40} = vdata; 86 let Inst{52-48} = srsrc{6-2}; 87 let Inst{54} = slc; 88 let Inst{55} = tfe; 89 let Inst{63-56} = soffset; 90} 91 92class SMEMe_vi <bits<8> op, bit imm> : Enc64 { 93 bits<7> sbase; 94 bits<7> sdst; 95 bits<1> glc; 96 97 let Inst{5-0} = sbase{6-1}; 98 let Inst{12-6} = sdst; 99 let Inst{16} = glc; 100 let Inst{17} = imm; 101 let Inst{25-18} = op; 102 let Inst{31-26} = 0x30; //encoding 103} 104 105class SMEM_IMMe_vi <bits<8> op> : SMEMe_vi<op, 1> { 106 bits<20> offset; 107 let Inst{51-32} = offset; 108} 109 110class SMEM_SOFFe_vi <bits<8> op> : SMEMe_vi<op, 0> { 111 bits<20> soff; 112 let Inst{51-32} = soff; 113} 114 115class VOP3a_vi <bits<10> op> : Enc64 { 116 bits<2> src0_modifiers; 117 bits<9> src0; 118 bits<2> src1_modifiers; 119 bits<9> src1; 120 bits<2> src2_modifiers; 121 bits<9> src2; 122 bits<1> clamp; 123 bits<2> omod; 124 125 let Inst{8} = src0_modifiers{1}; 126 let Inst{9} = src1_modifiers{1}; 127 let Inst{10} = src2_modifiers{1}; 128 let Inst{15} = clamp; 129 let Inst{25-16} = op; 130 let Inst{31-26} = 0x34; //encoding 131 let Inst{40-32} = src0; 132 let Inst{49-41} = src1; 133 let Inst{58-50} = src2; 134 let Inst{60-59} = omod; 135 let Inst{61} = src0_modifiers{0}; 136 let Inst{62} = src1_modifiers{0}; 137 let Inst{63} = src2_modifiers{0}; 138} 139 140class VOP3e_vi <bits<10> op> : VOP3a_vi <op> { 141 bits<8> vdst; 142 143 let Inst{7-0} = vdst; 144} 145 146// Encoding used for VOPC instructions encoded as VOP3 147// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst 148class VOP3ce_vi <bits<10> op> : VOP3a_vi <op> { 149 bits<8> sdst; 150 151 let Inst{7-0} = sdst; 152} 153 154class VOP3be_vi <bits<10> op> : Enc64 { 155 bits<8> vdst; 156 bits<2> src0_modifiers; 157 bits<9> src0; 158 bits<2> src1_modifiers; 159 bits<9> src1; 160 bits<2> src2_modifiers; 161 bits<9> src2; 162 bits<7> sdst; 163 bits<2> omod; 164 bits<1> clamp; 165 166 let Inst{7-0} = vdst; 167 let Inst{14-8} = sdst; 168 let Inst{15} = clamp; 169 let Inst{25-16} = op; 170 let Inst{31-26} = 0x34; //encoding 171 let Inst{40-32} = src0; 172 let Inst{49-41} = src1; 173 let Inst{58-50} = src2; 174 let Inst{60-59} = omod; 175 let Inst{61} = src0_modifiers{0}; 176 let Inst{62} = src1_modifiers{0}; 177 let Inst{63} = src2_modifiers{0}; 178} 179 180class VOP_DPP <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0> : 181 VOPAnyCommon <outs, ins, asm, pattern> { 182 let DPP = 1; 183 let Size = 8; 184 185 let AsmMatchConverter = !if(!eq(HasMods,1), "cvtDPP", ""); 186} 187 188class VOP_DPPe : Enc64 { 189 bits<2> src0_modifiers; 190 bits<8> src0; 191 bits<2> src1_modifiers; 192 bits<9> dpp_ctrl; 193 bits<1> bound_ctrl; 194 bits<4> bank_mask; 195 bits<4> row_mask; 196 197 let Inst{39-32} = src0; 198 let Inst{48-40} = dpp_ctrl; 199 let Inst{51} = bound_ctrl; 200 let Inst{52} = src0_modifiers{0}; // src0_neg 201 let Inst{53} = src0_modifiers{1}; // src0_abs 202 let Inst{54} = src1_modifiers{0}; // src1_neg 203 let Inst{55} = src1_modifiers{1}; // src1_abs 204 let Inst{59-56} = bank_mask; 205 let Inst{63-60} = row_mask; 206} 207 208class VOP1_DPPe <bits<8> op> : VOP_DPPe { 209 bits<8> vdst; 210 211 let Inst{8-0} = 0xfa; // dpp 212 let Inst{16-9} = op; 213 let Inst{24-17} = vdst; 214 let Inst{31-25} = 0x3f; //encoding 215} 216 217class VOP2_DPPe <bits<6> op> : VOP_DPPe { 218 bits<8> vdst; 219 bits<8> src1; 220 221 let Inst{8-0} = 0xfa; //dpp 222 let Inst{16-9} = src1; 223 let Inst{24-17} = vdst; 224 let Inst{30-25} = op; 225 let Inst{31} = 0x0; //encoding 226} 227 228class VOP_SDWA <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0> : 229 VOPAnyCommon <outs, ins, asm, pattern> { 230 let SDWA = 1; 231 let Size = 8; 232} 233 234class VOP_SDWAe : Enc64 { 235 bits<8> src0; 236 bits<3> src0_sel; 237 bits<2> src0_fmodifiers; // {abs,neg} 238 bits<1> src0_imodifiers; // sext 239 bits<3> src1_sel; 240 bits<2> src1_fmodifiers; 241 bits<1> src1_imodifiers; 242 bits<3> dst_sel; 243 bits<2> dst_unused; 244 bits<1> clamp; 245 246 let Inst{39-32} = src0; 247 let Inst{42-40} = dst_sel; 248 let Inst{44-43} = dst_unused; 249 let Inst{45} = clamp; 250 let Inst{50-48} = src0_sel; 251 let Inst{53-52} = src0_fmodifiers; 252 let Inst{51} = src0_imodifiers; 253 let Inst{58-56} = src1_sel; 254 let Inst{61-60} = src1_fmodifiers; 255 let Inst{59} = src1_imodifiers; 256} 257 258class VOP1_SDWAe <bits<8> op> : VOP_SDWAe { 259 bits<8> vdst; 260 261 let Inst{8-0} = 0xf9; // sdwa 262 let Inst{16-9} = op; 263 let Inst{24-17} = vdst; 264 let Inst{31-25} = 0x3f; // encoding 265} 266 267class VOP2_SDWAe <bits<6> op> : VOP_SDWAe { 268 bits<8> vdst; 269 bits<8> src1; 270 271 let Inst{8-0} = 0xf9; // sdwa 272 let Inst{16-9} = src1; 273 let Inst{24-17} = vdst; 274 let Inst{30-25} = op; 275 let Inst{31} = 0x0; // encoding 276} 277 278class VOPC_SDWAe <bits<8> op> : VOP_SDWAe { 279 bits<8> src1; 280 281 let Inst{8-0} = 0xf9; // sdwa 282 let Inst{16-9} = src1; 283 let Inst{24-17} = op; 284 let Inst{31-25} = 0x3e; // encoding 285 286 // VOPC disallows dst_sel and dst_unused as they have no effect on destination 287 let Inst{42-40} = 0x6; 288 let Inst{44-43} = 0x2; 289} 290 291class EXPe_vi : EXPe { 292 let Inst{31-26} = 0x31; //encoding 293} 294 295class VINTRPe_vi <bits<2> op> : VINTRPe <op> { 296 let Inst{31-26} = 0x35; // encoding 297} 298