| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_calcmaxspectralline.s | 44 VORR Q3, Q0, Q3
46 VORR Q3, Q1, Q3
|
| /external/libhevc/common/arm/ |
| D | ihevc_sao_band_offset_chroma.s | 169 VORR.U8 D4,D4,D13 @band_table.val[3] = vorr_u8(band_table.val[3], au1_cmp)
177 VORR.U8 D3,D3,D14 @band_table.val[2] = vorr_u8(band_table.val[2], au1_cmp)
187 VORR.U8 D2,D2,D15 @band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
196 VORR.U8 D1,D1,D16 @band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
243 VORR.U8 D12,D12,D17 @band_table.val[3] = vorr_u8(band_table.val[3], au1_cmp)
251 VORR.U8 D11,D11,D18 @band_table.val[2] = vorr_u8(band_table.val[2], au1_cmp)
261 VORR.U8 D10,D10,D19 @band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
271 VORR.U8 D9,D9,D20 @band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
|
| D | ihevc_sao_band_offset_luma.s | 153 VORR.U8 D4,D4,D12 @band_table.val[3] = vorr_u8(band_table.val[3], au1_cmp)
161 VORR.U8 D3,D3,D11 @band_table.val[2] = vorr_u8(band_table.val[2], au1_cmp)
171 VORR.U8 D2,D2,D10 @band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
181 VORR.U8 D1,D1,D9 @band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | vfcmp.ll | 87 ; ueq is implemented with VCGT/VCGT/VORR/VMVN
101 ; one is implemented with VCGT/VCGT/VORR
114 ; uno is implemented with VCGT/VCGE/VORR/VMVN
128 ; ord is implemented with VCGT/VCGE/VORR
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vfcmp.ll | 87 ; ueq is implemented with VCGT/VCGT/VORR/VMVN
101 ; one is implemented with VCGT/VCGT/VORR
114 ; uno is implemented with VCGT/VCGE/VORR/VMVN
128 ; ord is implemented with VCGT/VCGE/VORR
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | vfcmp.ll | 87 ; ueq is implemented with VCGT/VCGT/VORR/VMVN
101 ; one is implemented with VCGT/VCGT/VORR
114 ; uno is implemented with VCGT/VCGE/VORR/VMVN
128 ; ord is implemented with VCGT/VCGE/VORR
|
| /external/arm-neon-tests/ |
| D | ref-rvct-neon-nofp16.txt | 4213 VORR/VORRQ output:
4214 VORR/VORRQ:0:result_int8x8 [] = { fffffff2, fffffff3, fffffff2, fffffff3, fffffff6, fffffff7, fffff…
4215 VORR/VORRQ:1:result_int16x4 [] = { fffffffc, fffffffd, fffffffe, ffffffff, }
4216 VORR/VORRQ:2:result_int32x2 [] = { fffffff3, fffffff3, }
4217 VORR/VORRQ:3:result_int64x1 [] = { fffffffffffffff4, }
4218 VORR/VORRQ:4:result_uint8x8 [] = { f4, f5, f6, f7, f4, f5, f6, f7, }
4219 VORR/VORRQ:5:result_uint16x4 [] = { fffe, ffff, fffe, ffff, }
4220 VORR/VORRQ:6:result_uint32x2 [] = { fffffff8, fffffff9, }
4221 VORR/VORRQ:7:result_uint64x1 [] = { fffffffffffffff2, }
4222 VORR/VORRQ:8:result_poly8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
[all …]
|
| D | ref-rvct-neon.txt | 4745 VORR/VORRQ output:
4746 VORR/VORRQ:0:result_int8x8 [] = { fffffff2, fffffff3, fffffff2, fffffff3, fffffff6, fffffff7, fffff…
4747 VORR/VORRQ:1:result_int16x4 [] = { fffffffc, fffffffd, fffffffe, ffffffff, }
4748 VORR/VORRQ:2:result_int32x2 [] = { fffffff3, fffffff3, }
4749 VORR/VORRQ:3:result_int64x1 [] = { fffffffffffffff4, }
4750 VORR/VORRQ:4:result_uint8x8 [] = { f4, f5, f6, f7, f4, f5, f6, f7, }
4751 VORR/VORRQ:5:result_uint16x4 [] = { fffe, ffff, fffe, ffff, }
4752 VORR/VORRQ:6:result_uint32x2 [] = { fffffff8, fffffff9, }
4753 VORR/VORRQ:7:result_uint64x1 [] = { fffffffffffffff2, }
4754 VORR/VORRQ:8:result_poly8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
[all …]
|
| D | ref-rvct-all.txt | 4745 VORR/VORRQ output:
4746 VORR/VORRQ:0:result_int8x8 [] = { fffffff2, fffffff3, fffffff2, fffffff3, fffffff6, fffffff7, fffff…
4747 VORR/VORRQ:1:result_int16x4 [] = { fffffffc, fffffffd, fffffffe, ffffffff, }
4748 VORR/VORRQ:2:result_int32x2 [] = { fffffff3, fffffff3, }
4749 VORR/VORRQ:3:result_int64x1 [] = { fffffffffffffff4, }
4750 VORR/VORRQ:4:result_uint8x8 [] = { f4, f5, f6, f7, f4, f5, f6, f7, }
4751 VORR/VORRQ:5:result_uint16x4 [] = { fffe, ffff, fffe, ffff, }
4752 VORR/VORRQ:6:result_uint32x2 [] = { fffffff8, fffffff9, }
4753 VORR/VORRQ:7:result_uint64x1 [] = { fffffffffffffff2, }
4754 VORR/VORRQ:8:result_poly8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
[all …]
|
| D | expected_input4gcc-nofp16.txt | 4238 VORR/VORRQ output:
|
| D | expected_input4gcc.txt | 4554 VORR/VORRQ output:
|
| /external/v8/src/arm/ |
| D | assembler-arm.cc | 4192 enum BinaryBitwiseOp { VAND, VBIC, VBIF, VBIT, VBSL, VEOR, VORR, VORN }; enumerator
4214 case VORR: in EncodeNeonBinaryBitwiseOp()
4279 emit(EncodeNeonBinaryBitwiseOp(VORR, NEON_Q, dst.code(), src1.code(), in vorr()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 561 "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
|
| D | ARMScheduleR52.td | 815 def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "VORR", "VORN", "VREV")>;
|
| D | ARMScheduleA57.td | 1013 (instregex "VAND", "VBIC", "VMVN", "VORR", "VORN", "VEOR")>;
|
| D | ARMScheduleA9.td | 2426 // VADD/VAND/VORR/VEOR/VBIC/VORN/VBIT/VBIF/VBSL
|
| D | ARMInstrNEON.td | 5133 // VORR : Vector Bitwise OR
5945 // as their copies counterpart (VORR), so we should prefer rematerialization
7505 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 544 "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
|
| D | ARMScheduleA9.td | 2402 // VADD/VAND/VORR/VEOR/VBIC/VORN/VBIT/VBIF/VBSL
|
| D | ARMInstrNEON.td | 4859 // VORR : Vector Bitwise OR
5693 // as their copies counterpart (VORR), so we should prefer rematerialization
7141 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 803 def VORR : LOpInst<"vorr", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>;
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 3737 // VORR : Vector Bitwise OR
|