| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_calc_pre_twid.s | 59 VSHRN.S64 D12, Q6, #32
60 VSHRN.S64 D14, Q7, #32
61 VSHRN.S64 D16, Q8, #32
62 VSHRN.S64 D18, Q9, #32
63 VSHRN.S64 D20, Q10, #32
64 VSHRN.S64 D22, Q11, #32
65 VSHRN.S64 D24, Q12, #32
66 VSHRN.S64 D26, Q13, #32
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| D | ixheaacd_calc_post_twid.s | 52 VSHRN.S64 D6, Q4, #32
53 VSHRN.S64 D8, Q5, #32
54 VSHRN.S64 D10, Q6, #32
55 VSHRN.S64 D12, Q7, #32
56 VSHRN.S64 D7, Q8, #32
57 VSHRN.S64 D9, Q9, #32
58 VSHRN.S64 D11, Q10, #32
59 VSHRN.S64 D13, Q11, #32
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| D | ixheaacd_esbr_cos_sin_mod_loop2.s | 79 VSHRN.I64 D12, Q6, #32
80 VSHRN.I64 D14, Q7, #32
81 VSHRN.I64 D16, Q8, #32
110 VSHRN.I64 D12, Q6, #32
111 VSHRN.I64 D14, Q7, #32
112 VSHRN.I64 D16, Q8, #32
139 VSHRN.I64 D12, Q6, #32
140 VSHRN.I64 D14, Q7, #32
141 VSHRN.I64 D16, Q8, #32
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| D | ixheaacd_esbr_cos_sin_mod_loop1.s | 57 VSHRN.I64 D0, Q0, #32
58 VSHRN.I64 D2, Q1, #32
83 VSHRN.I64 D0, Q0, #32
84 VSHRN.I64 D2, Q1, #32
109 VSHRN.I64 D0, Q0, #32
110 VSHRN.I64 D2, Q1, #32
135 VSHRN.I64 D0, Q0, #32
136 VSHRN.I64 D2, Q1, #32
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| D | ixheaacd_mps_synt_pre_twiddle.s | 43 VSHRN.I64 D4, Q2, #31
44 VSHRN.I64 D6, Q3, #31
45 VSHRN.I64 D8, Q4, #31
46 VSHRN.I64 D10, Q5, #31
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| D | ixheaacd_mps_synt_post_twiddle.s | 43 VSHRN.I64 D4, Q2, #31
44 VSHRN.I64 D6, Q3, #31
45 VSHRN.I64 D8, Q4, #31
46 VSHRN.I64 D10, Q5, #31
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| D | ixheaacd_mps_synt_post_fft_twiddle.s | 48 VSHRN.S64 D8, Q4, #31
49 VSHRN.S64 D10, Q5, #31
50 VSHRN.S64 D12, Q6, #31
51 VSHRN.S64 D14, Q7, #31
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| D | ixheaacd_mps_synt_out_calc.s | 34 VSHRN.S64 D8, Q4, #31
35 VSHRN.S64 D9, Q5, #31
36 VSHRN.S64 D12, Q6, #31
37 VSHRN.S64 D13, Q7, #31
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| D | ixheaacd_esbr_qmfsyn64_winadd.s | 116 VSHRN.S64 D26 , Q13, #31
121 VSHRN.S64 D27 , Q14, #31
209 VSHRN.S64 D26 , Q13, #31
214 VSHRN.S64 D27 , Q14, #31
301 VSHRN.S64 D26 , Q13, #31
306 VSHRN.S64 D27 , Q14, #31
397 VSHRN.S64 D26 , Q13, #31
402 VSHRN.S64 D27, Q14, #31
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| D | ixheaacd_esbr_fwd_modulation.s | 93 VSHRN.I64 D0, Q0, #31
94 VSHRN.I64 D2, Q1, #31
|
| /external/libhevc/common/arm/ |
| D | ihevc_resi_trans.s | 1440 VSHRN.S32 D8,Q4,#SHIFT @NARROW R1
1443 VSHRN.S32 D9,Q6,#SHIFT @NARROW R2, dual issued in 2nd cycle
1481 VSHRN.S32 D8,Q9,#SHIFT @Shift by SHIFT
1501 VSHRN.S32 D9,Q12,#SHIFT @Shift by SHIFT
1553 VSHRN.S32 D26,Q9,#SHIFT
1554 VSHRN.S32 D27,Q12,#SHIFT
1598 VSHRN.S32 D22,Q9,#SHIFT
1601 VSHRN.S32 D23,Q10,#SHIFT
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 116 VSHRN, // ...right narrow enumerator
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| D | ARMInstrNEON.td | 78 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
4145 // VSHRN : Vector Shift Right and Narrow
4146 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
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| D | ARMISelLowering.cpp | 885 case ARMISD::VSHRN: return "ARMISD::VSHRN"; in getTargetNodeName()
7640 VShiftOpc = ARMISD::VSHRN; break; in PerformIntrinsicCombine()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 580 (instregex "VADDHN", "VSUBHN", "VSHRN")>;
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| D | ARMScheduleA57.td | 1116 (instregex "VMOVL", "VSHLi", "VSHLL", "VSHR(s|u)", "VSHRN")>;
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| D | ARMInstrNEON.td | 510 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
5741 // VSHRN : Vector Shift Right and Narrow
5742 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 563 (instregex "VADDHN", "VSUBHN", "VSHRN")>;
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| D | ARMInstrNEON.td | 520 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
5465 // VSHRN : Vector Shift Right and Narrow
5466 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
|