| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/ARM/ |
| D | tbl1.ll | 27 ; CHECK-NEXT: [[VTBL1:%.*]] = call <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8> [[VEC:%.*]], <8 x i8> …
28 ; CHECK-NEXT: ret <8 x i8> [[VTBL1]]
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 161 VTBL1, // 1-register shuffle with mask enumerator
|
| D | ARMISelDAGToDAG.cpp | 3141 case ARMISD::VTBL1: { in Select()
3150 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops.data(), Ops.size()); in Select()
|
| D | ARMISelLowering.cpp | 911 case ARMISD::VTBL1: return "ARMISD::VTBL1"; in getTargetNodeName()
4318 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, in LowerVECTOR_SHUFFLEv8i8()
|
| D | ARMInstrNEON.td | 4848 def VTBL1
|
| /external/arm-neon-tests/ |
| D | ref-rvct-neon-nofp16.txt | 6581 VTBL1 output:
6582 VTBL1:0:result_int8x8 [] = { 0, fffffff2, fffffff2, fffffff2, 0, 0, fffffff2, fffffff2, }
6583 VTBL1:1:result_int16x4 [] = { 3333, 3333, 3333, 3333, }
6584 VTBL1:2:result_int32x2 [] = { 33333333, 33333333, }
6585 VTBL1:3:result_int64x1 [] = { 3333333333333333, }
6586 VTBL1:4:result_uint8x8 [] = { 0, f3, f3, f3, 0, 0, f3, f3, }
6587 VTBL1:5:result_uint16x4 [] = { 3333, 3333, 3333, 3333, }
6588 VTBL1:6:result_uint32x2 [] = { 33333333, 33333333, }
6589 VTBL1:7:result_uint64x1 [] = { 3333333333333333, }
6590 VTBL1:8:result_poly8x8 [] = { 0, f3, f3, f3, 0, 0, f3, f3, }
[all …]
|
| D | ref-rvct-neon.txt | 7533 VTBL1 output:
7534 VTBL1:0:result_int8x8 [] = { 0, fffffff2, fffffff2, fffffff2, 0, 0, fffffff2, fffffff2, }
7535 VTBL1:1:result_int16x4 [] = { 3333, 3333, 3333, 3333, }
7536 VTBL1:2:result_int32x2 [] = { 33333333, 33333333, }
7537 VTBL1:3:result_int64x1 [] = { 3333333333333333, }
7538 VTBL1:4:result_uint8x8 [] = { 0, f3, f3, f3, 0, 0, f3, f3, }
7539 VTBL1:5:result_uint16x4 [] = { 3333, 3333, 3333, 3333, }
7540 VTBL1:6:result_uint32x2 [] = { 33333333, 33333333, }
7541 VTBL1:7:result_uint64x1 [] = { 3333333333333333, }
7542 VTBL1:8:result_poly8x8 [] = { 0, f3, f3, f3, 0, 0, f3, f3, }
[all …]
|
| D | ref-rvct-all.txt | 7533 VTBL1 output:
7534 VTBL1:0:result_int8x8 [] = { 0, fffffff2, fffffff2, fffffff2, 0, 0, fffffff2, fffffff2, }
7535 VTBL1:1:result_int16x4 [] = { 3333, 3333, 3333, 3333, }
7536 VTBL1:2:result_int32x2 [] = { 33333333, 33333333, }
7537 VTBL1:3:result_int64x1 [] = { 3333333333333333, }
7538 VTBL1:4:result_uint8x8 [] = { 0, f3, f3, f3, 0, 0, f3, f3, }
7539 VTBL1:5:result_uint16x4 [] = { 3333, 3333, 3333, 3333, }
7540 VTBL1:6:result_uint32x2 [] = { 33333333, 33333333, }
7541 VTBL1:7:result_uint64x1 [] = { 3333333333333333, }
7542 VTBL1:8:result_poly8x8 [] = { 0, f3, f3, f3, 0, 0, f3, f3, }
[all …]
|
| D | expected_input4gcc-nofp16.txt | 6784 VTBL1 output:
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 159 VTBL1, // 1-register shuffle with mask enumerator
|
| D | ARMISelDAGToDAG.cpp | 3693 case ARMISD::VTBL1: { in Select()
3699 ReplaceNode(N, CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops)); in Select()
|
| D | ARMISelLowering.cpp | 1214 case ARMISD::VTBL1: return "ARMISD::VTBL1"; in getTargetNodeName()
6191 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, in LowerVECTOR_SHUFFLEv8i8()
|
| D | ARMInstrNEON.td | 6442 def VTBL1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 191 VTBL1, // 1-register shuffle with mask enumerator
|
| D | ARMISelLowering.cpp | 1343 case ARMISD::VTBL1: return "ARMISD::VTBL1"; in getTargetNodeName()
3420 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
7016 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, in LowerVECTOR_SHUFFLEv8i8()
|
| D | ARMInstrNEON.td | 584 def NEONvtbl1 : SDNode<"ARMISD::VTBL1", SDTARMVTBL1>;
6717 def VTBL1
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmWriter.inc | 3191 424682U, // VTBL1
6411 336U, // VTBL1
8426 // VTBL1
|
| D | ARMGenSubtargetInfo.inc | 5251 { 0, 0, 0, 0, 0 }, // 500 VTBL1
6256 { 1, 103, 108, 2610, 2613 }, // 500 VTBL1
7261 { 1, 317, 319, 5538, 5541 }, // 500 VTBL1
11041 {DBGFIELD("VTBL1") 1, false, false, 17, 2, 3, 1, 73, 1}, // #500
12448 {DBGFIELD("VTBL1") 1, false, false, 20, 1, 3, 1, 0, 0}, // #500
13855 {DBGFIELD("VTBL1") 1, false, false, 18, 1, 16, 1, 74, 2}, // #500
15262 {DBGFIELD("VTBL1") 1, false, false, 43, 2, 2, 1, 0, 0}, // #500
|
| D | ARMGenFastISel.inc | 3321 // FastEmit functions for ARMISD::VTBL1.
3327 return fastEmitInst_rr(ARM::VTBL1, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4795 case ARMISD::VTBL1: return fastEmit_ARMISD_VTBL1_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
|
| D | ARMGenMCCodeEmitter.inc | 2684 UINT64_C(4088399872), // VTBL1
6963 case ARM::VTBL1:
13957 Feature_HasNEON | 0, // VTBL1 = 2671
|
| D | ARMGenInstrInfo.inc | 2686 VTBL1 = 2671,
3746 VTBL1 = 500,
7366 …D::Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #2671 = VTBL1
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 729 def VTBL1 : WInst<"vtbl1", "ddt", "UccPc">;
|
| /external/capstone/arch/ARM/ |
| D | ARMGenAsmWriter.inc | 2227 2910244U, // VTBL1
5020 304U, // VTBL1
7467 // VTBL1
|
| D | ARMGenInstrInfo.inc | 5404 …<MCID_Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2210 = VTBL1
|
| D | ARMGenDisassemblerTables.inc | 3770 /* 7652 */ MCD_OPC_Decode, 162, 17, 132, 1, // Opcode: VTBL1
|