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Searched refs:Vd (Results 1 – 25 of 334) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td218 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
220 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
226 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
228 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
251 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
253 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
259 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
261 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
284 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
286 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
[all …]
DARMInstrFormats.td1636 bits<5> Vd;
1640 let Inst{22} = Vd{4};
1641 let Inst{15-12} = Vd{3-0};
1706 bits<5> Vd;
1709 let Inst{15-12} = Vd{3-0};
1710 let Inst{22} = Vd{4};
1732 bits<5> Vd;
1735 let Inst{15-12} = Vd{3-0};
1736 let Inst{22} = Vd{4};
1756 bits<5> Vd;
[all …]
/external/v8/src/arm/
Ddisasm-arm.cc90 void FormatNeonList(int Vd, int type);
400 void Decoder::FormatNeonList(int Vd, int type) { in FormatNeonList() argument
403 "{d%d}", Vd); in FormatNeonList()
406 "{d%d, d%d}", Vd, Vd + 1); in FormatNeonList()
409 "{d%d, d%d, d%d}", Vd, Vd + 1, Vd + 2); in FormatNeonList()
412 "{d%d, d%d, d%d, d%d}", Vd, Vd + 1, Vd + 2, Vd + 3); in FormatNeonList()
1609 int Vd = instr->VFPNRegValue(kSimd128Precision); in DecodeTypeVFP() local
1611 "vdup.%i q%d, %s", size, Vd, rt_name); in DecodeTypeVFP()
1899 int Vd, Vm, Vn; in DecodeSpecialCondition() local
1901 Vd = instr->VFPDRegValue(kDoublePrecision); in DecodeSpecialCondition()
[all …]
Dsimulator-arm.cc3945 void Widen(Simulator* simulator, int Vd, int Vm) { in Widen() argument
3953 simulator->set_neon_register(Vd, dst); in Widen()
3957 void Abs(Simulator* simulator, int Vd, int Vm) { in Abs() argument
3964 simulator->set_neon_register<T, SIZE>(Vd, src); in Abs()
3968 void Neg(Simulator* simulator, int Vd, int Vm) { in Neg() argument
3975 simulator->set_neon_register<T, SIZE>(Vd, src); in Neg()
3979 void SaturatingNarrow(Simulator* simulator, int Vd, int Vm) { in SaturatingNarrow() argument
3987 simulator->set_neon_register<U, kDoubleSize>(Vd, dst); in SaturatingNarrow()
3991 void AddSaturate(Simulator* simulator, int Vd, int Vm, int Vn) { in AddSaturate() argument
3999 simulator->set_neon_register(Vd, src1); in AddSaturate()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrNEON.td265 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
296 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
306 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
316 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
326 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
336 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
348 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
[all …]
DARMInstrFormats.td2110 bits<5> Vd;
2114 let Inst{22} = Vd{4};
2115 let Inst{15-12} = Vd{3-0};
2180 bits<5> Vd;
2183 let Inst{15-12} = Vd{3-0};
2184 let Inst{22} = Vd{4};
2206 bits<5> Vd;
2209 let Inst{15-12} = Vd{3-0};
2210 let Inst{22} = Vd{4};
2220 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
306 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
316 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
326 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
336 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
346 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
368 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
[all …]
DARMInstrFormats.td2078 bits<5> Vd;
2082 let Inst{22} = Vd{4};
2083 let Inst{15-12} = Vd{3-0};
2148 bits<5> Vd;
2151 let Inst{15-12} = Vd{3-0};
2152 let Inst{22} = Vd{4};
2174 bits<5> Vd;
2177 let Inst{15-12} = Vd{3-0};
2178 let Inst{22} = Vd{4};
2188 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenGlobalISel.inc1391 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1471 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1519 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1559 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1595 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
[all …]
DARMGenMCCodeEmitter.inc4900 // op: Vd
4921 // op: Vd
4933 // op: Vd
4964 // op: Vd
4976 // op: Vd
4993 // op: Vd
5012 // op: Vd
5037 // op: Vd
5053 // op: Vd
5069 // op: Vd
[all …]
/external/clang/include/clang/Analysis/Analyses/
DThreadSafetyTIL.h364 Variable(const Variable &Vd, SExpr *D) // rewrite constructor in Variable() argument
365 : SExpr(Vd), Name(Vd.Name), Definition(D), Cvdecl(Vd.Cvdecl) { in Variable()
366 Flags = Vd.kind(); in Variable()
659 Function(Variable *Vd, SExpr *Bd) in Function() argument
660 : SExpr(COP_Function), VarDecl(Vd), Body(Bd) { in Function()
661 Vd->setKind(Variable::VK_Fun); in Function()
663 Function(const Function &F, Variable *Vd, SExpr *Bd) // rewrite constructor in Function() argument
664 : SExpr(F), VarDecl(Vd), Body(Bd) { in Function()
665 Vd->setKind(Variable::VK_Fun); in Function()
710 SFunction(Variable *Vd, SExpr *B) in SFunction() argument
[all …]
/external/clang/lib/Analysis/
DThreadSafety.cpp243 bool containsMutexDecl(FactManager &FM, const ValueDecl* Vd) const { in containsMutexDecl()
245 return FM[ID].valueDecl() == Vd; in containsMutexDecl()
275 BeforeInfo* insertAttrExprs(const ValueDecl* Vd,
278 BeforeInfo *getBeforeInfoForDecl(const ValueDecl *Vd,
281 void checkBeforeAfter(const ValueDecl* Vd,
967 BeforeSet::BeforeInfo* BeforeSet::insertAttrExprs(const ValueDecl* Vd, in insertAttrExprs() argument
974 std::unique_ptr<BeforeInfo> &InfoPtr = BMap[Vd]; in insertAttrExprs()
980 for (Attr* At : Vd->attrs()) { in insertAttrExprs()
1008 ArgInfo->Vect.push_back(Vd); in insertAttrExprs()
1022 BeforeSet::getBeforeInfoForDecl(const ValueDecl *Vd, in getBeforeInfoForDecl() argument
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2849 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2850 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2851 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2852 (NOTv16i8 V128:$Vd, V128:$Vn)>;
4018 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
4021 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
4024 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
4027 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
4030 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
4033 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrAlias.td502 // maps Vd = #0 to Vd = vxor(Vd, Vd)
503 def : InstAlias<"$Vd = #0",
504 (V6_vxor VectorRegs:$Vd, VectorRegs:$Vd, VectorRegs:$Vd)>,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td3113 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
3114 (NOTv8i8 V64:$Vd, V64:$Vn)>;
3115 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
3116 (NOTv16i8 V128:$Vd, V128:$Vn)>;
4349 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
4352 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
4355 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
4358 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
4361 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
4364 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
[all …]
DAArch64InstrFormats.td5521 def : InstAlias<asm # "\t$Vd.4h, $Vn.4h, #0",
5522 (!cast<Instruction>(NAME # v4i16rz) V64:$Vd, V64:$Vn), 0>;
5523 def : InstAlias<asm # "\t$Vd.8h, $Vn.8h, #0",
5524 (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>;
5526 def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0",
5527 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
5528 def : InstAlias<asm # "\t$Vd.4s, $Vn.4s, #0",
5529 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
5530 def : InstAlias<asm # "\t$Vd.2d, $Vn.2d, #0",
5531 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
[all …]
/external/capstone/arch/ARM/
DARMDisassembler.c1290 unsigned Vd = fieldFromInstruction_4(Val, 8, 5); in DecodeSPRRegListOperand() local
1294 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand()
1295 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeSPRRegListOperand()
1300 if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1303 if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1315 unsigned Vd = fieldFromInstruction_4(Val, 8, 5); in DecodeDPRRegListOperand() local
1319 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { in DecodeDPRRegListOperand()
1320 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeDPRRegListOperand()
1326 if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeDPRRegListOperand()
1330 if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeDPRRegListOperand()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1248 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeSPRRegListOperand() local
1252 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand()
1253 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeSPRRegListOperand()
1258 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1261 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1272 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeDPRRegListOperand() local
1276 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { in DecodeDPRRegListOperand()
1277 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeDPRRegListOperand()
1283 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeDPRRegListOperand()
1286 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeDPRRegListOperand()
[all …]
/external/honggfuzz/examples/apache-httpd/corpus_http1/
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/external/v8/benchmarks/
Draytrace.js481 var Vd = this.position.dot(ray.direction);
482 if(Vd == 0) return info; // no intersection
484 var t = -(this.position.dot(ray.position) + this.d) / Vd;
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1249 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeSPRRegListOperand() local
1253 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand()
1254 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeSPRRegListOperand()
1259 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1262 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1273 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeDPRRegListOperand() local
1277 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { in DecodeDPRRegListOperand()
1278 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeDPRRegListOperand()
1284 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeDPRRegListOperand()
1287 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeDPRRegListOperand()
[all …]
/external/honggfuzz/examples/apache-httpd/corpus_http2/
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