| /external/v8/src/mips/ |
| D | constants-mips.h | 574 WSBH = ((0U << 3) + 2), enumerator
1722 case WSBH: in InstructionType()
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| D | disasm-mips.cc | 1541 case WSBH: { in DecodeTypeRegisterSPECIAL3()
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| D | assembler-mips.cc | 2570 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, WSBH, BSHFL); in wsbh()
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| D | simulator-mips.cc | 4200 case WSBH: { in DecodeTypeRegisterSPECIAL3()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 595 WSBH = ((0U << 3) + 2), enumerator
1787 case WSBH: in InstructionType()
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| D | disasm-mips64.cc | 1785 case WSBH: { in DecodeTypeRegisterSPECIAL3()
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| D | assembler-mips64.cc | 2943 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, WSBH, BSHFL); in wsbh()
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| D | simulator-mips64.cc | 4305 case WSBH: { in DecodeTypeRegisterSPECIAL3()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1361 emitInst(Mips::WSBH, DestReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1381 emitInst(Mips::WSBH, TempReg).addReg(SrcReg); in fastLowerIntrinsicCall()
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| D | MipsInstrInfo.td | 1995 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>,
2647 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1577 emitInst(Mips::WSBH, DestReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1597 emitInst(Mips::WSBH, TempReg).addReg(SrcReg); in fastLowerIntrinsicCall()
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| D | MipsScheduleP5600.td | 173 def : InstRW<[P5600WriteAL2ShadowMov], (instrs EHB, RDHWR, WSBH)>;
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| D | MipsInstrInfo.td | 2361 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>,
3230 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>, ISA_MIPS32R2;
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 737 {DBGFIELD("WSBH") 1, false, false, 1, 2, 1, 1, 0, 0}, // #462
1757 {DBGFIELD("WSBH") 1, false, false, 1, 2, 2, 1, 0, 0}, // #462
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| D | MipsGenMCCodeEmitter.inc | 2624 UINT64_C(2080374944), // WSBH
4609 case Mips::WSBH: {
10350 Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotInMicroMips | 0, // WSBH = 2611
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| D | MipsGenInstrInfo.inc | 2626 WSBH = 2611,
3119 WSBH = 462,
6671 …611, 2, 1, 4, 462, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2611 = WSBH
10287 { Mips::WSBH, Mips::WSBH, Mips::WSBH_MM },
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| D | MipsGenAsmWriter.inc | 3839 21729U, // WSBH
6470 0U, // WSBH
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| D | MipsGenGlobalISel.inc | 15529 …// (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i…
15531 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH,
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| D | MipsGenDisassemblerTables.inc | 5875 /* 15549 */ MCD::OPC_Decode, 179, 20, 190, 2, // Opcode: WSBH
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| D | MipsGenAsmMatcher.inc | 7638 …{ 9532 /* wsbh */, Mips::WSBH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_…
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| D | MipsGenDAGISel.inc | 26841 /* 50438*/ OPC_EmitNode1, TARGET_VAL(Mips::WSBH), 0,
26847 … // Dst: (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1713 21141U, // WSBH
3427 0U, // WSBH
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| D | MipsGenDisassemblerTables.inc | 3379 /* 12209 */ MCD_OPC_Decode, 160, 13, 182, 1, // Opcode: WSBH
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