/external/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeVectorOps.cpp | 520 EVT WideVT = TLI.getPointerTy(DAG.getDataLayout()); in ExpandLoad() local 522 assert(WideVT.isRound() && in ExpandLoad() 525 assert(WideVT.bitsGE(SrcEltVT) && in ExpandLoad() 528 unsigned WideBytes = WideVT.getStoreSize(); in ExpandLoad() 538 ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR, in ExpandLoad() 545 EVT LoadVT = WideVT; in ExpandLoad() 550 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR, in ExpandLoad() 570 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, dl, WideVT); in ExpandLoad() 574 unsigned WideBits = WideVT.getSizeInBits(); in ExpandLoad() 581 BitOffset, dl, TLI.getShiftAmountTy(WideVT, DAG.getDataLayout())); in ExpandLoad() [all …]
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D | LegalizeDAG.cpp | 3378 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); in ExpandNode() local 3394 } else if (TLI.isTypeLegal(WideVT)) { in ExpandNode() 3395 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); in ExpandNode() 3396 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); in ExpandNode() 3397 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); in ExpandNode() 3408 if (WideVT == MVT::i16) in ExpandNode() 3410 else if (WideVT == MVT::i32) in ExpandNode() 3412 else if (WideVT == MVT::i64) in ExpandNode() 3414 else if (WideVT == MVT::i128) in ExpandNode() 3435 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl); in ExpandNode()
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D | LegalizeTypes.cpp | 1137 EVT WideVT = EVT::getVectorVT(*DAG.getContext(), BoolVT.getScalarType(), in WidenTargetBoolean() local 1139 Bool = ModifyToType(Bool, WideVT, WithZeroes); in WidenTargetBoolean()
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D | LegalizeVectorTypes.cpp | 2904 EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in WidenVecRes_MGATHER() local 2907 unsigned NumElts = WideVT.getVectorNumElements(); in WidenVecRes_MGATHER() 2911 Mask = WidenTargetBoolean(Mask, WideVT, true); in WidenVecRes_MGATHER() 2920 SDValue Res = DAG.getMaskedGather(DAG.getVTList(WideVT, MVT::Other), in WidenVecRes_MGATHER() 3342 EVT WideVT = WideVal.getValueType(); in WidenVecOp_MSCATTER() local 3347 Mask = WidenTargetBoolean(Mask, WideVT, true); in WidenVecOp_MSCATTER()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeVectorOps.cpp | 582 EVT WideVT = TLI.getPointerTy(DAG.getDataLayout()); in ExpandLoad() local 584 assert(WideVT.isRound() && in ExpandLoad() 587 assert(WideVT.bitsGE(SrcEltVT) && in ExpandLoad() 590 unsigned WideBytes = WideVT.getStoreSize(); in ExpandLoad() 600 DAG.getLoad(WideVT, dl, Chain, BasePTR, in ExpandLoad() 605 EVT LoadVT = WideVT; in ExpandLoad() 611 DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR, in ExpandLoad() 628 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, dl, WideVT); in ExpandLoad() 632 unsigned WideBits = WideVT.getSizeInBits(); in ExpandLoad() 639 BitOffset, dl, TLI.getShiftAmountTy(WideVT, DAG.getDataLayout())); in ExpandLoad() [all …]
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D | LegalizeVectorTypes.cpp | 3028 EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in WidenVecRes_MGATHER() local 3033 unsigned NumElts = WideVT.getVectorNumElements(); in WidenVecRes_MGATHER() 3039 WideVT.getVectorNumElements()); in WidenVecRes_MGATHER() 3049 SDValue Res = DAG.getMaskedGather(DAG.getVTList(WideVT, MVT::Other), in WidenVecRes_MGATHER() 3254 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0); in WidenVSELECTAndMask() local 3255 if (ScalarBits_ToMask >= WideVT.getScalarSizeInBits()) in WidenVSELECTAndMask() 3256 MaskVT = WideVT; in WidenVSELECTAndMask() 3536 EVT WideVT = EVT::getVectorVT(*DAG.getContext(), EltVT, in WidenVecOp_Convert() local 3538 if (TLI.isTypeLegal(WideVT)) { in WidenVecOp_Convert() 3539 SDValue Res = DAG.getNode(Opcode, dl, WideVT, InOp); in WidenVecOp_Convert() [all …]
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D | LegalizeDAG.cpp | 3528 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); in ExpandNode() local 3544 } else if (TLI.isTypeLegal(WideVT)) { in ExpandNode() 3545 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); in ExpandNode() 3546 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); in ExpandNode() 3547 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); in ExpandNode() 3558 if (WideVT == MVT::i16) in ExpandNode() 3560 else if (WideVT == MVT::i32) in ExpandNode() 3562 else if (WideVT == MVT::i64) in ExpandNode() 3564 else if (WideVT == MVT::i128) in ExpandNode() 3598 Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl); in ExpandNode() [all …]
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D | DAGCombiner.cpp | 7764 EVT WideVT = N1.getValueType().changeVectorElementTypeToInteger(); in visitVSELECT() local 7767 unsigned WideWidth = WideVT.getScalarSizeInBits(); in visitVSELECT() 7772 TLI.isLoadExtLegalOrCustom(LoadExtOpcode, WideVT, NarrowVT) && in visitVSELECT() 7773 TLI.isOperationLegalOrCustom(ISD::SETCC, WideVT)) { in visitVSELECT() 7779 SDValue WideLHS = DAG.getNode(ExtOpcode, DL, WideVT, LHS); in visitVSELECT() 7780 SDValue WideRHS = DAG.getNode(ExtOpcode, DL, WideVT, RHS); in visitVSELECT() 7781 EVT WideSetCCVT = getSetCCResultType(WideVT); in visitVSELECT()
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZISelLowering.cpp | 3213 EVT WideVT = MVT::i32; in lowerATOMIC_LOAD_OP() local 3214 if (NarrowVT == WideVT) in lowerATOMIC_LOAD_OP() 3240 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift); in lowerATOMIC_LOAD_OP() 3244 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT, in lowerATOMIC_LOAD_OP() 3245 DAG.getConstant(0, DL, WideVT), BitShift); in lowerATOMIC_LOAD_OP() 3253 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP() 3254 DAG.getConstant(32 - BitSize, DL, WideVT)); in lowerATOMIC_LOAD_OP() 3257 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP() 3258 DAG.getConstant(uint32_t(-1) >> BitSize, DL, WideVT)); in lowerATOMIC_LOAD_OP() 3261 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other); in lowerATOMIC_LOAD_OP() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
D | SystemZISelLowering.cpp | 3437 EVT WideVT = MVT::i32; in lowerATOMIC_LOAD_OP() local 3438 if (NarrowVT == WideVT) in lowerATOMIC_LOAD_OP() 3464 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift); in lowerATOMIC_LOAD_OP() 3468 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT, in lowerATOMIC_LOAD_OP() 3469 DAG.getConstant(0, DL, WideVT), BitShift); in lowerATOMIC_LOAD_OP() 3477 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP() 3478 DAG.getConstant(32 - BitSize, DL, WideVT)); in lowerATOMIC_LOAD_OP() 3481 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP() 3482 DAG.getConstant(uint32_t(-1) >> BitSize, DL, WideVT)); in lowerATOMIC_LOAD_OP() 3485 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other); in lowerATOMIC_LOAD_OP() [all …]
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
D | LegalizeDAG.cpp | 3601 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); in ExpandNode() local 3619 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); in ExpandNode() 3620 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); in ExpandNode() 3621 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); in ExpandNode() 3632 if (WideVT == MVT::i16) in ExpandNode() 3634 else if (WideVT == MVT::i32) in ExpandNode() 3636 else if (WideVT == MVT::i64) in ExpandNode() 3638 else if (WideVT == MVT::i128) in ExpandNode() 3655 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl); in ExpandNode()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | AArch64ISelDAGToDAG.cpp | 1352 EVT WideVT = RegSeq.getOperand(1)->getValueType(0); in SelectLoadLane() local 1356 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane() 1404 EVT WideVT = RegSeq.getOperand(1)->getValueType(0); in SelectPostLoadLane() local 1408 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, in SelectPostLoadLane()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelDAGToDAG.cpp | 1284 EVT WideVT = RegSeq.getOperand(1)->getValueType(0); in SelectLoadLane() local 1288 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane() 1336 EVT WideVT = RegSeq.getOperand(1)->getValueType(0); in SelectPostLoadLane() local 1340 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, in SelectPostLoadLane()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 16987 MVT WideVT = ExtVT; in LowerZERO_EXTEND_Mask() local 16993 WideVT = MVT::getVectorVT(ExtVT.getVectorElementType(), in LowerZERO_EXTEND_Mask() 16997 SDValue One = DAG.getConstant(1, DL, WideVT); in LowerZERO_EXTEND_Mask() 16998 SDValue Zero = getZeroVector(WideVT, Subtarget, DAG, DL); in LowerZERO_EXTEND_Mask() 17000 SDValue SelectedVal = DAG.getSelect(DL, WideVT, In, One, Zero); in LowerZERO_EXTEND_Mask() 17004 WideVT = MVT::getVectorVT(MVT::i8, NumElts); in LowerZERO_EXTEND_Mask() 17005 SelectedVal = DAG.getNode(ISD::TRUNCATE, DL, WideVT, SelectedVal); in LowerZERO_EXTEND_Mask() 17009 if (WideVT != VT) in LowerZERO_EXTEND_Mask() 17920 EVT WideVT = WideVal.getValueType(); in EmitTest() local 17936 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) { in EmitTest() [all …]
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/external/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 2965 EVT WideVT = MVT::i128; in LowerUMULO_SMULO() local 2980 RTLIB::MUL_I128, WideVT, in LowerUMULO_SMULO()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 2999 EVT WideVT = MVT::i128; in LowerUMULO_SMULO() local 3014 RTLIB::MUL_I128, WideVT, in LowerUMULO_SMULO()
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 14816 EVT WideVT = WideVal.getValueType(); in EmitTest() local 14832 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) { in EmitTest() 28028 EVT WideVT = N0->getOperand(0)->getValueType(0); in WidenMaskArithmetic() local 28029 if (WideVT != VT) in WidenMaskArithmetic() 28042 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT)) in WidenMaskArithmetic() 28048 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(), in WidenMaskArithmetic() 28050 N1 = DAG.getSplatBuildVector(WideVT, DL, N1); in WidenMaskArithmetic() 28056 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1); in WidenMaskArithmetic()
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