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Searched refs:X86 (Results 1 – 25 of 1218) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrFoldTables.cpp37 { X86::ADC16ri, X86::ADC16mi, 0 },
38 { X86::ADC16ri8, X86::ADC16mi8, 0 },
39 { X86::ADC16rr, X86::ADC16mr, 0 },
40 { X86::ADC32ri, X86::ADC32mi, 0 },
41 { X86::ADC32ri8, X86::ADC32mi8, 0 },
42 { X86::ADC32rr, X86::ADC32mr, 0 },
43 { X86::ADC64ri32, X86::ADC64mi32, 0 },
44 { X86::ADC64ri8, X86::ADC64mi8, 0 },
45 { X86::ADC64rr, X86::ADC64mr, 0 },
46 { X86::ADC8ri, X86::ADC8mi, 0 },
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DX86InstrInfo.cpp81 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
82 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
83 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
84 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
85 X86::CATCHRET, in X86InstrInfo()
86 (STI.is64Bit() ? X86::RETQ : X86::RETL)), in X86InstrInfo()
96 case X86::MOVSX16rr8: in isCoalescableExtInstr()
97 case X86::MOVZX16rr8: in isCoalescableExtInstr()
98 case X86::MOVSX32rr8: in isCoalescableExtInstr()
99 case X86::MOVZX32rr8: in isCoalescableExtInstr()
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DX86MacroFusion.cpp42 : static_cast<unsigned>(X86::INSTRUCTION_LIST_END); in shouldScheduleAdjacent()
48 case X86::JE_1: in shouldScheduleAdjacent()
49 case X86::JNE_1: in shouldScheduleAdjacent()
50 case X86::JL_1: in shouldScheduleAdjacent()
51 case X86::JLE_1: in shouldScheduleAdjacent()
52 case X86::JG_1: in shouldScheduleAdjacent()
53 case X86::JGE_1: in shouldScheduleAdjacent()
56 case X86::JB_1: in shouldScheduleAdjacent()
57 case X86::JBE_1: in shouldScheduleAdjacent()
58 case X86::JA_1: in shouldScheduleAdjacent()
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DX86FloatingPoint.cpp132 static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums"); in calcLiveInMask()
133 if (Reg >= X86::FP0 && Reg <= X86::FP6) { in calcLiveInMask()
134 Mask |= 1 << (Reg - X86::FP0); in calcLiveInMask()
206 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
242 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); in moveToTop()
252 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); in duplicateToTop()
296 return X86::RFP80RegClass.contains(DstReg) || in isFPCopy()
297 X86::RFP80RegClass.contains(SrcReg); in isFPCopy()
312 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); in getFPReg()
313 return Reg - X86::FP0; in getFPReg()
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DX86SpeculativeLoadHardening.cpp256 BuildMI(&MBB, DebugLoc(), TII.get(X86::JMP_1)).addMBB(&OldLayoutSucc); in splitEdge()
379 if (MI.getOpcode() == X86::LFENCE) in hasVulnerableLoad()
387 if (MI.getOpcode() == X86::MFENCE) in hasVulnerableLoad()
410 PS.emplace(MF, &X86::GR64_NOSPRegClass); in runOnMachineFunction()
443 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::MOV64ri32), PS->PoisonReg) in runOnMachineFunction()
456 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::LFENCE)); in runOnMachineFunction()
476 unsigned PredStateSubReg = MRI->createVirtualRegister(&X86::GR32RegClass); in runOnMachineFunction()
477 auto ZeroI = BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::MOV32r0), in runOnMachineFunction()
481 ZeroI->findRegisterDefOperand(X86::EFLAGS); in runOnMachineFunction()
485 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::SUBREG_TO_REG), in runOnMachineFunction()
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DX86MCInstLower.cpp106 !(Inst.getFlags() & X86::NO_SCHED_INFO)); in EmitAndCountInstruction()
291 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
309 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw in SimplifyMOVSX()
310 if (Op0 == X86::AX && Op1 == X86::AL) in SimplifyMOVSX()
311 NewOpcode = X86::CBW; in SimplifyMOVSX()
313 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl in SimplifyMOVSX()
314 if (Op0 == X86::EAX && Op1 == X86::AX) in SimplifyMOVSX()
315 NewOpcode = X86::CWDE; in SimplifyMOVSX()
317 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq in SimplifyMOVSX()
318 if (Op0 == X86::RAX && Op1 == X86::EAX) in SimplifyMOVSX()
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenEVEX2VEXTables.inc3 |* X86 EVEX2VEX tables *|
9 // X86 EVEX encoded instructions that have a VEX 128 encoding
13 { X86::VADDPDZ128rm, X86::VADDPDrm },
14 { X86::VADDPDZ128rr, X86::VADDPDrr },
15 { X86::VADDPSZ128rm, X86::VADDPSrm },
16 { X86::VADDPSZ128rr, X86::VADDPSrr },
17 { X86::VADDSDZrm, X86::VADDSDrm },
18 { X86::VADDSDZrm_Int, X86::VADDSDrm_Int },
19 { X86::VADDSDZrr, X86::VADDSDrr },
20 { X86::VADDSDZrr_Int, X86::VADDSDrr_Int },
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DX86GenRegisterInfo.inc18 namespace X86 {
299 } // end namespace X86
303 namespace X86 {
393 } // end namespace X86
398 namespace X86 {
411 } // end namespace X86
1085 { X86::AH },
1086 { X86::AL },
1087 { X86::BH },
1088 { X86::BL },
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/external/llvm/lib/Target/X86/
DX86InstrInfo.cpp116 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
117 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
118 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
119 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
120 X86::CATCHRET, in X86InstrInfo()
121 (STI.is64Bit() ? X86::RETQ : X86::RETL)), in X86InstrInfo()
125 { X86::ADC32ri, X86::ADC32mi, 0 }, in X86InstrInfo()
126 { X86::ADC32ri8, X86::ADC32mi8, 0 }, in X86InstrInfo()
127 { X86::ADC32rr, X86::ADC32mr, 0 }, in X86InstrInfo()
128 { X86::ADC64ri32, X86::ADC64mi32, 0 }, in X86InstrInfo()
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DX86FloatingPoint.cpp129 if (LI.PhysReg < X86::FP0 || LI.PhysReg > X86::FP6) in calcLiveInMask()
131 Mask |= 1 << (LI.PhysReg - X86::FP0); in calcLiveInMask()
197 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
226 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); in moveToTop()
236 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); in duplicateToTop()
280 return X86::RFP80RegClass.contains(DstReg) || in isFPCopy()
281 X86::RFP80RegClass.contains(SrcReg); in isFPCopy()
296 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); in getFPReg()
297 return Reg - X86::FP0; in getFPReg()
308 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!"); in runOnMachineFunction()
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/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp70 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { in initLLVMToSEHAndCVRegMapping()
77 X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, in initLLVMToSEHAndCVRegMapping()
78 X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX, in initLLVMToSEHAndCVRegMapping()
79 X86::SP, X86::BP, X86::SI, X86::DI, X86::EAX, X86::ECX, in initLLVMToSEHAndCVRegMapping()
80 X86::EDX, X86::EBX, X86::ESP, X86::EBP, X86::ESI, X86::EDI, in initLLVMToSEHAndCVRegMapping()
86 MRI->mapLLVMRegToCVReg(X86::EFLAGS, 34); in initLLVMToSEHAndCVRegMapping()
91 MRI->mapLLVMRegToCVReg(X86::FP0 + I, FP0Start + I); in initLLVMToSEHAndCVRegMapping()
96 MRI->mapLLVMRegToCVReg(X86::XMM0 + I, CVXMM0Start + I); in initLLVMToSEHAndCVRegMapping()
101 MRI->mapLLVMRegToCVReg(X86::XMM8 + I, CVXMM8Start + I); in initLLVMToSEHAndCVRegMapping()
108 X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX, in initLLVMToSEHAndCVRegMapping()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.cpp56 ? X86::RIP : X86::EIP, in X86RegisterInfo()
69 StackPtr = X86::RSP; in X86RegisterInfo()
70 FramePtr = X86::RBP; in X86RegisterInfo()
73 StackPtr = X86::ESP; in X86RegisterInfo()
74 FramePtr = X86::EBP; in X86RegisterInfo()
82 case X86::EBX: case X86::RBX: return 1; in getCompactUnwindRegNum()
83 case X86::ECX: case X86::R12: return 2; in getCompactUnwindRegNum()
84 case X86::EDX: case X86::R13: return 3; in getCompactUnwindRegNum()
85 case X86::EDI: case X86::R14: return 4; in getCompactUnwindRegNum()
86 case X86::ESI: case X86::R15: return 5; in getCompactUnwindRegNum()
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DX86InstrInfo.cpp88 ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
89 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
91 ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
92 : X86::ADJCALLSTACKUP32)), in X86InstrInfo()
96 { X86::ADC32ri, X86::ADC32mi, 0 }, in X86InstrInfo()
97 { X86::ADC32ri8, X86::ADC32mi8, 0 }, in X86InstrInfo()
98 { X86::ADC32rr, X86::ADC32mr, 0 }, in X86InstrInfo()
99 { X86::ADC64ri32, X86::ADC64mi32, 0 }, in X86InstrInfo()
100 { X86::ADC64ri8, X86::ADC64mi8, 0 }, in X86InstrInfo()
101 { X86::ADC64rr, X86::ADC64mr, 0 }, in X86InstrInfo()
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DX86GenRegisterInfo.inc17 namespace X86 {
184 namespace X86 {
249 const unsigned AH_Overlaps[] = { X86::AH, X86::AX, X86::EAX, X86::RAX, 0 };
250 const unsigned AL_Overlaps[] = { X86::AL, X86::AX, X86::EAX, X86::RAX, 0 };
251 const unsigned AX_Overlaps[] = { X86::AX, X86::AH, X86::AL, X86::EAX, X86::RAX, 0 };
252 const unsigned BH_Overlaps[] = { X86::BH, X86::BX, X86::EBX, X86::RBX, 0 };
253 const unsigned BL_Overlaps[] = { X86::BL, X86::BX, X86::EBX, X86::RBX, 0 };
254 const unsigned BP_Overlaps[] = { X86::BP, X86::BPL, X86::EBP, X86::RBP, 0 };
255 const unsigned BPL_Overlaps[] = { X86::BPL, X86::BP, X86::EBP, X86::RBP, 0 };
256 const unsigned BX_Overlaps[] = { X86::BX, X86::BH, X86::BL, X86::EBX, X86::RBX, 0 };
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DX86FloatingPoint.cpp119 unsigned Reg = *I - X86::FP0; in calcLiveInMask()
222 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0; in getSTReg()
251 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); in moveToTop()
260 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); in duplicateToTop()
317 return X86::RFP80RegClass.contains(DstReg) || in isFPCopy()
318 X86::RFP80RegClass.contains(SrcReg); in isFPCopy()
331 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); in getFPReg()
332 return Reg - X86::FP0; in getFPReg()
343 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!"); in runOnMachineFunction()
345 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) { in runOnMachineFunction()
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DX86GenSubtargetInfo.inc13 namespace X86 {
55 { "3dnow", "Enable 3DNow! instructions", X86::Feature3DNow, X86::FeatureMMX },
56 { "3dnowa", "Enable 3DNow! Athlon instructions", X86::Feature3DNowA, X86::Feature3DNow },
57 { "64bit", "Support 64-bit instructions", X86::Feature64Bit, X86::FeatureCMOV },
58 { "64bit-mode", "64-bit mode (x86_64)", X86::Mode64Bit, 0ULL },
59 { "aes", "Enable AES instructions", X86::FeatureAES, 0ULL },
60 { "avx", "Enable AVX instructions", X86::FeatureAVX, 0ULL },
61 { "bmi", "Support BMI instructions", X86::FeatureBMI, 0ULL },
62 { "clmul", "Enable carry-less multiplication instructions", X86::FeatureCLMUL, 0ULL },
63 { "cmov", "Enable conditional move instructions", X86::FeatureCMOV, 0ULL },
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DX86MCInstLower.cpp240 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
273 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortMoveForm()
346 case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand. in Lower()
349 case X86::LEA64r: in Lower()
350 case X86::LEA16r: in Lower()
351 case X86::LEA32r: in Lower()
353 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands && in Lower()
355 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && in Lower()
358 case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break; in Lower()
359 case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break; in Lower()
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DX86GenAsmMatcher.inc1792 Inst.addOperand(MCOperand::CreateReg(X86::ST0));
1795 Inst.addOperand(MCOperand::CreateReg(X86::ST1));
2623 case X86::AL: OpKind = MCK_AL; break;
2624 case X86::DL: OpKind = MCK_GR8_ABCD_L; break;
2625 case X86::CL: OpKind = MCK_CL; break;
2626 case X86::BL: OpKind = MCK_GR8_ABCD_L; break;
2627 case X86::SIL: OpKind = MCK_GR8; break;
2628 case X86::DIL: OpKind = MCK_GR8; break;
2629 case X86::BPL: OpKind = MCK_GR8; break;
2630 case X86::SPL: OpKind = MCK_GR8; break;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp74 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { in initLLVMToSEHAndCVRegMapping()
84 { codeview::RegisterId::CVRegAL, X86::AL}, in initLLVMToSEHAndCVRegMapping()
85 { codeview::RegisterId::CVRegCL, X86::CL}, in initLLVMToSEHAndCVRegMapping()
86 { codeview::RegisterId::CVRegDL, X86::DL}, in initLLVMToSEHAndCVRegMapping()
87 { codeview::RegisterId::CVRegBL, X86::BL}, in initLLVMToSEHAndCVRegMapping()
88 { codeview::RegisterId::CVRegAH, X86::AH}, in initLLVMToSEHAndCVRegMapping()
89 { codeview::RegisterId::CVRegCH, X86::CH}, in initLLVMToSEHAndCVRegMapping()
90 { codeview::RegisterId::CVRegDH, X86::DH}, in initLLVMToSEHAndCVRegMapping()
91 { codeview::RegisterId::CVRegBH, X86::BH}, in initLLVMToSEHAndCVRegMapping()
92 { codeview::RegisterId::CVRegAX, X86::AX}, in initLLVMToSEHAndCVRegMapping()
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DX86AsmBackend.cpp42 case X86::reloc_riprel_4byte: in getFixupKindLog2Size()
43 case X86::reloc_riprel_4byte_relax: in getFixupKindLog2Size()
44 case X86::reloc_riprel_4byte_relax_rex: in getFixupKindLog2Size()
45 case X86::reloc_riprel_4byte_movq_load: in getFixupKindLog2Size()
46 case X86::reloc_signed_4byte: in getFixupKindLog2Size()
47 case X86::reloc_signed_4byte_relax: in getFixupKindLog2Size()
48 case X86::reloc_global_offset_table: in getFixupKindLog2Size()
49 case X86::reloc_branch_4byte_pcrel: in getFixupKindLog2Size()
56 case X86::reloc_global_offset_table8: in getFixupKindLog2Size()
77 return X86::NumTargetFixupKinds; in getNumFixupKinds()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp113 namespace X86 { namespace
158 if (FB[X86::Mode16Bit]) { in X86GenericDisassembler()
161 } else if (FB[X86::Mode32Bit]) { in X86GenericDisassembler()
164 } else if (FB[X86::Mode64Bit]) { in X86GenericDisassembler()
238 unsigned Flags = X86::IP_NO_PREFIX; in getInstruction()
240 Flags |= X86::IP_HAS_AD_SIZE; in getInstruction()
243 Flags |= X86::IP_HAS_OP_SIZE; in getInstruction()
245 Flags |= X86::IP_HAS_REPEAT_NE; in getInstruction()
249 Flags |= X86::IP_HAS_REPEAT; in getInstruction()
251 Flags |= X86::IP_HAS_LOCK; in getInstruction()
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/external/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp112 namespace X86 { namespace
157 if (FB[X86::Mode16Bit]) { in X86GenericDisassembler()
160 } else if (FB[X86::Mode32Bit]) { in X86GenericDisassembler()
163 } else if (FB[X86::Mode64Bit]) { in X86GenericDisassembler()
249 #define ENTRY(x) X86::x, in translateRegister()
302 X86::CS,
303 X86::SS,
304 X86::DS,
305 X86::ES,
306 X86::FS,
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/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp145 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX; in getX86RegNum()
146 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX; in getX86RegNum()
147 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX; in getX86RegNum()
148 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX; in getX86RegNum()
149 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH: in getX86RegNum()
151 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH: in getX86RegNum()
153 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH: in getX86RegNum()
155 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH: in getX86RegNum()
158 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: in getX86RegNum()
160 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: in getX86RegNum()
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DX86AsmBackend.cpp46 case X86::reloc_riprel_4byte: in getFixupKindLog2Size()
47 case X86::reloc_riprel_4byte_movq_load: in getFixupKindLog2Size()
48 case X86::reloc_signed_4byte: in getFixupKindLog2Size()
49 case X86::reloc_global_offset_table: in getFixupKindLog2Size()
71 return X86::NumTargetFixupKinds; in getNumFixupKinds()
75 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = { in getFixupKindInfo()
121 case X86::JAE_1: return X86::JAE_4; in getRelaxedOpcodeBranch()
122 case X86::JA_1: return X86::JA_4; in getRelaxedOpcodeBranch()
123 case X86::JBE_1: return X86::JBE_4; in getRelaxedOpcodeBranch()
124 case X86::JB_1: return X86::JB_4; in getRelaxedOpcodeBranch()
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dgpr-to-mask.ll2 …86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq < %s | FileCheck %s --check-prefix=X86-64
3 …=i386-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq < %s | FileCheck %s --check-prefix=X86-32
6 ; X86-64-LABEL: test_fcmp_storefloat:
7 ; X86-64: # %bb.0: # %entry
8 ; X86-64-NEXT: testb $1, %dil
9 ; X86-64-NEXT: je .LBB0_2
10 ; X86-64-NEXT: # %bb.1: # %if
11 ; X86-64-NEXT: vcmpeqss %xmm3, %xmm2, %k1
12 ; X86-64-NEXT: jmp .LBB0_3
13 ; X86-64-NEXT: .LBB0_2: # %else
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