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Searched refs:XADD (Results 1 – 22 of 22) sorted by relevance

/external/llvm/lib/Target/BPF/
DBPFInstrInfo.td473 class XADD<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
494 def XADD32 : XADD<0, "xadd32", atomic_load_add_32>;
495 def XADD64 : XADD<3, "xadd64", atomic_load_add_64>;
496 // undefined def XADD16 : XADD<1, "xadd16", atomic_load_add_16>;
497 // undefined def XADD8 : XADD<2, "xadd8", atomic_load_add_8>;
/external/elfutils/libcpu/
Dbpf_disasm.c70 #define XADD(T, S) "lock *(" #T " *)(" REG(1) OFF(3) ") += " S macro
423 code_fmt = XADD(u32, REG(2)); in bpf_disasm()
426 code_fmt = XADD(u64, REG(2)); in bpf_disasm()
/external/llvm/lib/TableGen/
DTGLexer.h50 XConcat, XADD, XAND, XSRA, XSRL, XSHL, XListConcat, XStrConcat, XCast, enumerator
DTGLexer.cpp473 .Case("add", tgtok::XADD) in LexExclaim()
DTGParser.cpp872 case tgtok::XADD: in ParseOperation()
890 case tgtok::XADD: Code = BinOpInit::ADD; Type = IntRecTy::get(); break; in ParseOperation()
1438 case tgtok::XADD: in ParseSimpleValue()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/TableGen/
DTGLexer.h50 XConcat, XADD, XAND, XOR, XSRA, XSRL, XSHL, XListConcat, XStrConcat, XCast, enumerator
DTGLexer.cpp482 .Case("add", tgtok::XADD) in LexExclaim()
DTGParser.cpp1026 case tgtok::XADD: in ParseOperation()
1048 case tgtok::XADD: Code = BinOpInit::ADD; break; in ParseOperation()
1078 case tgtok::XADD: in ParseOperation()
1921 case tgtok::XADD: in ParseSimpleValue()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/
DBPFInstrInfo.td549 class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
565 def XADD32 : XADD<BPF_W, "u32", atomic_load_add_32>;
566 def XADD64 : XADD<BPF_DW, "u64", atomic_load_add_64>;
567 // undefined def XADD16 : XADD<1, "xadd16", atomic_load_add_16>;
568 // undefined def XADD8 : XADD<2, "xadd8", atomic_load_add_8>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ScheduleAtom.td568 "XADD(8|16|32|64)rr",
585 def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm",
DX86ScheduleZnver1.td809 // XADD.
810 def : InstRW<[WriteMicrocoded], (instregex "XADD(8|16|32|64)rm")>;
DX86SchedSandyBridge.td1004 def: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>;
DX86SchedSkylakeClient.td1238 def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;
DX86SchedBroadwell.td1157 def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
DX86SchedHaswell.td1227 def: InstRW<[HWWriteResGroup47], (instregex "XADD(8|16|32|64)rm")>;
DX86SchedSkylakeServer.td1508 def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
/external/bcc/src/lua/bpf/
Dbuiltins.lua123 e.emit(BPF.XADD + BPF.STX + const_width[w], dst_reg, src_reg, off or 0, 0)
Dbpf.lua1286 if mode == BPF.XADD then cls = 5 end -- The only mode
/external/llvm/lib/Target/X86/
DX86SchedHaswell.td1007 // XADD.
1011 def : InstRW<[WriteXADD], (instregex "XADD(8|16|32|64)rm")>;
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DAtomics.rst438 uses ``XCHG``, ``atomicrmw add`` and ``atomicrmw sub`` use ``XADD``, and all
/external/llvm/docs/
DAtomics.rst438 uses ``XCHG``, ``atomicrmw add`` and ``atomicrmw sub`` use ``XADD``, and all
/external/syzkaller/pkg/ifuzz/gen/
Dall-enc-instructions.txt9932 ICLASS : XADD
9943 ICLASS : XADD
9970 ICLASS : XADD
9982 ICLASS : XADD