1//=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the machine model for Sandy Bridge to support instruction 11// scheduling and other instruction cost heuristics. 12// 13// Note that we define some instructions here that are not supported by SNB, 14// but we still have to define them because SNB is the default subtarget for 15// X86. These instructions are tagged with a comment `Unsupported = 1`. 16// 17//===----------------------------------------------------------------------===// 18 19def SandyBridgeModel : SchedMachineModel { 20 // All x86 instructions are modeled as a single micro-op, and SB can decode 4 21 // instructions per cycle. 22 // FIXME: Identify instructions that aren't a single fused micro-op. 23 let IssueWidth = 4; 24 let MicroOpBufferSize = 168; // Based on the reorder buffer. 25 let LoadLatency = 5; 26 let MispredictPenalty = 16; 27 28 // Based on the LSD (loop-stream detector) queue size. 29 let LoopMicroOpBufferSize = 28; 30 31 // This flag is set to allow the scheduler to assign 32 // a default model to unrecognized opcodes. 33 let CompleteModel = 0; 34} 35 36let SchedModel = SandyBridgeModel in { 37 38// Sandy Bridge can issue micro-ops to 6 different ports in one cycle. 39 40// Ports 0, 1, and 5 handle all computation. 41def SBPort0 : ProcResource<1>; 42def SBPort1 : ProcResource<1>; 43def SBPort5 : ProcResource<1>; 44 45// Ports 2 and 3 are identical. They handle loads and the address half of 46// stores. 47def SBPort23 : ProcResource<2>; 48 49// Port 4 gets the data half of stores. Store data can be available later than 50// the store address, but since we don't model the latency of stores, we can 51// ignore that. 52def SBPort4 : ProcResource<1>; 53 54// Many micro-ops are capable of issuing on multiple ports. 55def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; 56def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>; 57def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; 58def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; 59 60// 54 Entry Unified Scheduler 61def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> { 62 let BufferSize=54; 63} 64 65// Integer division issued on port 0. 66def SBDivider : ProcResource<1>; 67// FP division and sqrt on port 0. 68def SBFPDivider : ProcResource<1>; 69 70// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 71// cycles after the memory operand. 72def : ReadAdvance<ReadAfterLd, 5>; 73 74// Many SchedWrites are defined in pairs with and without a folded load. 75// Instructions with folded loads are usually micro-fused, so they only appear 76// as two micro-ops when queued in the reservation station. 77// This multiclass defines the resource usage for variants with and without 78// folded loads. 79multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW, 80 list<ProcResourceKind> ExePorts, 81 int Lat, list<int> Res = [1], int UOps = 1, 82 int LoadLat = 5> { 83 // Register variant is using a single cycle on ExePort. 84 def : WriteRes<SchedRW, ExePorts> { 85 let Latency = Lat; 86 let ResourceCycles = Res; 87 let NumMicroOps = UOps; 88 } 89 90 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 91 // the latency (default = 5). 92 def : WriteRes<SchedRW.Folded, !listconcat([SBPort23], ExePorts)> { 93 let Latency = !add(Lat, LoadLat); 94 let ResourceCycles = !listconcat([1], Res); 95 let NumMicroOps = !add(UOps, 1); 96 } 97} 98 99// A folded store needs a cycle on port 4 for the store data, and an extra port 100// 2/3 cycle to recompute the address. 101def : WriteRes<WriteRMW, [SBPort23,SBPort4]>; 102 103def : WriteRes<WriteStore, [SBPort23, SBPort4]>; 104def : WriteRes<WriteStoreNT, [SBPort23, SBPort4]>; 105def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 5; } 106def : WriteRes<WriteMove, [SBPort015]>; 107def : WriteRes<WriteZero, []>; 108 109// Arithmetic. 110defm : SBWriteResPair<WriteALU, [SBPort015], 1>; 111defm : SBWriteResPair<WriteADC, [SBPort05,SBPort015], 2, [1,1], 2>; 112defm : SBWriteResPair<WriteIMul, [SBPort1], 3>; 113defm : SBWriteResPair<WriteIMul64, [SBPort1], 3>; 114 115defm : X86WriteRes<WriteBSWAP32, [SBPort1], 1, [1], 1>; 116defm : X86WriteRes<WriteBSWAP64, [SBPort1,SBPort05], 2, [1,1], 2>; 117 118defm : SBWriteResPair<WriteDiv8, [SBPort0, SBDivider], 25, [1, 10]>; 119defm : SBWriteResPair<WriteDiv16, [SBPort0, SBDivider], 25, [1, 10]>; 120defm : SBWriteResPair<WriteDiv32, [SBPort0, SBDivider], 25, [1, 10]>; 121defm : SBWriteResPair<WriteDiv64, [SBPort0, SBDivider], 25, [1, 10]>; 122defm : SBWriteResPair<WriteIDiv8, [SBPort0, SBDivider], 25, [1, 10]>; 123defm : SBWriteResPair<WriteIDiv16, [SBPort0, SBDivider], 25, [1, 10]>; 124defm : SBWriteResPair<WriteIDiv32, [SBPort0, SBDivider], 25, [1, 10]>; 125defm : SBWriteResPair<WriteIDiv64, [SBPort0, SBDivider], 25, [1, 10]>; 126 127def : WriteRes<WriteIMulH, []> { let Latency = 3; } 128 129// SHLD/SHRD. 130defm : X86WriteRes<WriteSHDrri, [SBPort05, SBPort015], 2, [1, 1], 2>; 131defm : X86WriteRes<WriteSHDrrcl,[SBPort05, SBPort015], 4, [3, 1], 4>; 132defm : X86WriteRes<WriteSHDmri, [SBPort4,SBPort23,SBPort05,SBPort015], 8, [1, 2, 1, 1], 5>; 133defm : X86WriteRes<WriteSHDmrcl,[SBPort4,SBPort23,SBPort05,SBPort015], 10, [1, 2, 3, 1], 7>; 134 135defm : SBWriteResPair<WriteShift, [SBPort05], 1>; 136defm : SBWriteResPair<WriteJump, [SBPort5], 1>; 137defm : SBWriteResPair<WriteCRC32, [SBPort1], 3, [1], 1, 5>; 138 139defm : SBWriteResPair<WriteCMOV, [SBPort05,SBPort015], 2, [1,1], 2>; // Conditional move. 140defm : SBWriteResPair<WriteCMOV2, [SBPort05,SBPort015], 3, [2,1], 3>; // Conditional (CF + ZF flag) move. 141defm : X86WriteRes<WriteFCMOV, [SBPort5,SBPort05], 3, [2,1], 3>; // x87 conditional move. 142def : WriteRes<WriteSETCC, [SBPort05]>; // Setcc. 143def : WriteRes<WriteSETCCStore, [SBPort05,SBPort4,SBPort23]> { 144 let Latency = 2; 145 let NumMicroOps = 3; 146} 147def : WriteRes<WriteLAHFSAHF, [SBPort05]>; 148def : WriteRes<WriteBitTest,[SBPort05]>; 149 150// This is for simple LEAs with one or two input operands. 151// The complex ones can only execute on port 1, and they require two cycles on 152// the port to read all inputs. We don't model that. 153def : WriteRes<WriteLEA, [SBPort01]>; 154 155// Bit counts. 156defm : SBWriteResPair<WriteBSF, [SBPort1], 3, [1], 1, 5>; 157defm : SBWriteResPair<WriteBSR, [SBPort1], 3, [1], 1, 5>; 158defm : SBWriteResPair<WriteLZCNT, [SBPort1], 3, [1], 1, 5>; 159defm : SBWriteResPair<WriteTZCNT, [SBPort1], 3, [1], 1, 5>; 160defm : SBWriteResPair<WritePOPCNT, [SBPort1], 3, [1], 1, 6>; 161 162// BMI1 BEXTR, BMI2 BZHI 163// NOTE: These don't exist on Sandy Bridge. Ports are guesses. 164defm : SBWriteResPair<WriteBEXTR, [SBPort05,SBPort1], 2, [1,1], 2>; 165defm : SBWriteResPair<WriteBZHI, [SBPort1], 1>; 166 167// Scalar and vector floating point. 168defm : X86WriteRes<WriteFLD0, [SBPort5], 1, [1], 1>; 169defm : X86WriteRes<WriteFLD1, [SBPort0,SBPort5], 1, [1,1], 2>; 170defm : X86WriteRes<WriteFLDC, [SBPort0,SBPort1], 1, [1,1], 2>; 171defm : X86WriteRes<WriteFLoad, [SBPort23], 5, [1], 1>; 172defm : X86WriteRes<WriteFLoadX, [SBPort23], 6, [1], 1>; 173defm : X86WriteRes<WriteFLoadY, [SBPort23], 7, [1], 1>; 174defm : X86WriteRes<WriteFMaskedLoad, [SBPort23,SBPort05], 8, [1,2], 3>; 175defm : X86WriteRes<WriteFMaskedLoadY, [SBPort23,SBPort05], 9, [1,2], 3>; 176defm : X86WriteRes<WriteFStore, [SBPort23,SBPort4], 1, [1,1], 1>; 177defm : X86WriteRes<WriteFStoreX, [SBPort23,SBPort4], 1, [1,1], 1>; 178defm : X86WriteRes<WriteFStoreY, [SBPort23,SBPort4], 1, [1,1], 1>; 179defm : X86WriteRes<WriteFStoreNT, [SBPort23,SBPort4], 1, [1,1], 1>; 180defm : X86WriteRes<WriteFStoreNTX, [SBPort23,SBPort4], 1, [1,1], 1>; 181defm : X86WriteRes<WriteFStoreNTY, [SBPort23,SBPort4], 1, [1,1], 1>; 182defm : X86WriteRes<WriteFMaskedStore, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 183defm : X86WriteRes<WriteFMaskedStoreY, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 184defm : X86WriteRes<WriteFMove, [SBPort5], 1, [1], 1>; 185defm : X86WriteRes<WriteFMoveX, [SBPort5], 1, [1], 1>; 186defm : X86WriteRes<WriteFMoveY, [SBPort5], 1, [1], 1>; 187defm : X86WriteRes<WriteEMMS, [SBPort015], 31, [31], 31>; 188 189defm : SBWriteResPair<WriteFAdd, [SBPort1], 3, [1], 1, 6>; 190defm : SBWriteResPair<WriteFAddX, [SBPort1], 3, [1], 1, 6>; 191defm : SBWriteResPair<WriteFAddY, [SBPort1], 3, [1], 1, 7>; 192defm : SBWriteResPair<WriteFAddZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 193defm : SBWriteResPair<WriteFAdd64, [SBPort1], 3, [1], 1, 6>; 194defm : SBWriteResPair<WriteFAdd64X, [SBPort1], 3, [1], 1, 6>; 195defm : SBWriteResPair<WriteFAdd64Y, [SBPort1], 3, [1], 1, 7>; 196defm : SBWriteResPair<WriteFAdd64Z, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 197 198defm : SBWriteResPair<WriteFCmp, [SBPort1], 3, [1], 1, 6>; 199defm : SBWriteResPair<WriteFCmpX, [SBPort1], 3, [1], 1, 6>; 200defm : SBWriteResPair<WriteFCmpY, [SBPort1], 3, [1], 1, 7>; 201defm : SBWriteResPair<WriteFCmpZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 202defm : SBWriteResPair<WriteFCmp64, [SBPort1], 3, [1], 1, 6>; 203defm : SBWriteResPair<WriteFCmp64X, [SBPort1], 3, [1], 1, 6>; 204defm : SBWriteResPair<WriteFCmp64Y, [SBPort1], 3, [1], 1, 7>; 205defm : SBWriteResPair<WriteFCmp64Z, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 206 207defm : SBWriteResPair<WriteFCom, [SBPort1], 3>; 208 209defm : SBWriteResPair<WriteFMul, [SBPort0], 5, [1], 1, 6>; 210defm : SBWriteResPair<WriteFMulX, [SBPort0], 5, [1], 1, 6>; 211defm : SBWriteResPair<WriteFMulY, [SBPort0], 5, [1], 1, 7>; 212defm : SBWriteResPair<WriteFMulZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 213defm : SBWriteResPair<WriteFMul64, [SBPort0], 5, [1], 1, 6>; 214defm : SBWriteResPair<WriteFMul64X, [SBPort0], 5, [1], 1, 6>; 215defm : SBWriteResPair<WriteFMul64Y, [SBPort0], 5, [1], 1, 7>; 216defm : SBWriteResPair<WriteFMul64Z, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 217 218defm : SBWriteResPair<WriteFDiv, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 219defm : SBWriteResPair<WriteFDivX, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 220defm : SBWriteResPair<WriteFDivY, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; 221defm : SBWriteResPair<WriteFDivZ, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; // Unsupported = 1 222defm : SBWriteResPair<WriteFDiv64, [SBPort0,SBFPDivider], 22, [1,22], 1, 6>; 223defm : SBWriteResPair<WriteFDiv64X, [SBPort0,SBFPDivider], 22, [1,22], 1, 6>; 224defm : SBWriteResPair<WriteFDiv64Y, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; 225defm : SBWriteResPair<WriteFDiv64Z, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; // Unsupported = 1 226 227defm : SBWriteResPair<WriteFRcp, [SBPort0], 5, [1], 1, 6>; 228defm : SBWriteResPair<WriteFRcpX, [SBPort0], 5, [1], 1, 6>; 229defm : SBWriteResPair<WriteFRcpY, [SBPort0,SBPort05], 7, [2,1], 3, 7>; 230defm : SBWriteResPair<WriteFRcpZ, [SBPort0,SBPort05], 7, [2,1], 3, 7>; // Unsupported = 1 231 232defm : SBWriteResPair<WriteFRsqrt, [SBPort0], 5, [1], 1, 6>; 233defm : SBWriteResPair<WriteFRsqrtX,[SBPort0], 5, [1], 1, 6>; 234defm : SBWriteResPair<WriteFRsqrtY,[SBPort0,SBPort05], 7, [2,1], 3, 7>; 235defm : SBWriteResPair<WriteFRsqrtZ,[SBPort0,SBPort05], 7, [2,1], 3, 7>; // Unsupported = 1 236 237defm : SBWriteResPair<WriteFSqrt, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 238defm : SBWriteResPair<WriteFSqrtX, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 239defm : SBWriteResPair<WriteFSqrtY, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; 240defm : SBWriteResPair<WriteFSqrtZ, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; // Unsupported = 1 241defm : SBWriteResPair<WriteFSqrt64, [SBPort0,SBFPDivider], 21, [1,21], 1, 6>; 242defm : SBWriteResPair<WriteFSqrt64X, [SBPort0,SBFPDivider], 21, [1,21], 1, 6>; 243defm : SBWriteResPair<WriteFSqrt64Y, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; 244defm : SBWriteResPair<WriteFSqrt64Z, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; // Unsupported = 1 245defm : SBWriteResPair<WriteFSqrt80, [SBPort0,SBFPDivider], 24, [1,24], 1, 6>; 246 247defm : SBWriteResPair<WriteDPPD, [SBPort0,SBPort1,SBPort5], 9, [1,1,1], 3, 6>; 248defm : SBWriteResPair<WriteDPPS, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 6>; 249defm : SBWriteResPair<WriteDPPSY, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 7>; 250defm : SBWriteResPair<WriteDPPSZ, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 7>; // Unsupported = 1 251defm : SBWriteResPair<WriteFSign, [SBPort5], 1>; 252defm : SBWriteResPair<WriteFRnd, [SBPort1], 3, [1], 1, 6>; 253defm : SBWriteResPair<WriteFRndY, [SBPort1], 3, [1], 1, 7>; 254defm : SBWriteResPair<WriteFRndZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 255defm : SBWriteResPair<WriteFLogic, [SBPort5], 1, [1], 1, 6>; 256defm : SBWriteResPair<WriteFLogicY, [SBPort5], 1, [1], 1, 7>; 257defm : SBWriteResPair<WriteFLogicZ, [SBPort5], 1, [1], 1, 7>; // Unsupported = 1 258defm : SBWriteResPair<WriteFTest, [SBPort0], 1, [1], 1, 6>; 259defm : SBWriteResPair<WriteFTestY, [SBPort0], 1, [1], 1, 7>; 260defm : SBWriteResPair<WriteFTestZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1 261defm : SBWriteResPair<WriteFShuffle, [SBPort5], 1, [1], 1, 6>; 262defm : SBWriteResPair<WriteFShuffleY,[SBPort5], 1, [1], 1, 7>; 263defm : SBWriteResPair<WriteFShuffleZ,[SBPort5], 1, [1], 1, 7>; // Unsupported = 1 264defm : SBWriteResPair<WriteFVarShuffle, [SBPort5], 1, [1], 1, 6>; 265defm : SBWriteResPair<WriteFVarShuffleY,[SBPort5], 1, [1], 1, 7>; 266defm : SBWriteResPair<WriteFVarShuffleZ,[SBPort5], 1, [1], 1, 7>; // Unsupported = 1 267defm : SBWriteResPair<WriteFBlend, [SBPort05], 1, [1], 1, 6>; 268defm : SBWriteResPair<WriteFBlendY, [SBPort05], 1, [1], 1, 7>; 269defm : SBWriteResPair<WriteFBlendZ, [SBPort05], 1, [1], 1, 7>; // Unsupported = 1 270defm : SBWriteResPair<WriteFVarBlend, [SBPort05], 2, [2], 2, 6>; 271defm : SBWriteResPair<WriteFVarBlendY,[SBPort05], 2, [2], 2, 7>; 272defm : SBWriteResPair<WriteFVarBlendZ,[SBPort05], 2, [2], 2, 7>; // Unsupported = 1 273 274// Conversion between integer and float. 275defm : SBWriteResPair<WriteCvtSS2I, [SBPort0,SBPort1], 5, [1,1], 2>; 276defm : SBWriteResPair<WriteCvtPS2I, [SBPort1], 3, [1], 1, 6>; 277defm : SBWriteResPair<WriteCvtPS2IY, [SBPort1], 3, [1], 1, 7>; 278defm : SBWriteResPair<WriteCvtPS2IZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 279defm : SBWriteResPair<WriteCvtSD2I, [SBPort0,SBPort1], 5, [1,1], 2>; 280defm : SBWriteResPair<WriteCvtPD2I, [SBPort1,SBPort5], 4, [1,1], 2, 6>; 281defm : X86WriteRes<WriteCvtPD2IY, [SBPort1,SBPort5], 4, [1,1], 2>; 282defm : X86WriteRes<WriteCvtPD2IZ, [SBPort1,SBPort5], 4, [1,1], 2>; // Unsupported = 1 283defm : X86WriteRes<WriteCvtPD2IYLd, [SBPort1,SBPort5,SBPort23], 11, [1,1,1], 3>; 284defm : X86WriteRes<WriteCvtPD2IZLd, [SBPort1,SBPort5,SBPort23], 11, [1,1,1], 3>; // Unsupported = 1 285 286defm : X86WriteRes<WriteCvtI2SS, [SBPort1,SBPort5], 5, [1,2], 3>; 287defm : X86WriteRes<WriteCvtI2SSLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; 288defm : SBWriteResPair<WriteCvtI2PS, [SBPort1], 3, [1], 1, 6>; 289defm : SBWriteResPair<WriteCvtI2PSY, [SBPort1], 3, [1], 1, 7>; 290defm : SBWriteResPair<WriteCvtI2PSZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 291defm : X86WriteRes<WriteCvtI2SD, [SBPort1,SBPort5], 4, [1,1], 2>; 292defm : X86WriteRes<WriteCvtI2PD, [SBPort1,SBPort5], 4, [1,1], 2>; 293defm : X86WriteRes<WriteCvtI2PDY, [SBPort1,SBPort5], 4, [1,1], 2>; 294defm : X86WriteRes<WriteCvtI2PDZ, [SBPort1,SBPort5], 4, [1,1], 2>; // Unsupported = 1 295defm : X86WriteRes<WriteCvtI2SDLd, [SBPort1,SBPort23], 9, [1,1], 2>; 296defm : X86WriteRes<WriteCvtI2PDLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; 297defm : X86WriteRes<WriteCvtI2PDYLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; 298defm : X86WriteRes<WriteCvtI2PDZLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; // Unsupported = 1 299 300defm : SBWriteResPair<WriteCvtSS2SD, [SBPort0], 1, [1], 1, 6>; 301defm : X86WriteRes<WriteCvtPS2PD, [SBPort0,SBPort5], 2, [1,1], 2>; 302defm : X86WriteRes<WriteCvtPS2PDY, [SBPort0,SBPort5], 2, [1,1], 2>; 303defm : X86WriteRes<WriteCvtPS2PDZ, [SBPort0,SBPort5], 2, [1,1], 2>; // Unsupported = 1 304defm : X86WriteRes<WriteCvtPS2PDLd, [SBPort0,SBPort23], 7, [1,1], 2>; 305defm : X86WriteRes<WriteCvtPS2PDYLd, [SBPort0,SBPort23], 7, [1,1], 2>; 306defm : X86WriteRes<WriteCvtPS2PDZLd, [SBPort0,SBPort23], 7, [1,1], 2>; // Unsupported = 1 307defm : SBWriteResPair<WriteCvtSD2SS, [SBPort1,SBPort5], 4, [1,1], 2, 6>; 308defm : SBWriteResPair<WriteCvtPD2PS, [SBPort1,SBPort5], 4, [1,1], 2, 6>; 309defm : SBWriteResPair<WriteCvtPD2PSY, [SBPort1,SBPort5], 4, [1,1], 2, 7>; 310defm : SBWriteResPair<WriteCvtPD2PSZ, [SBPort1,SBPort5], 4, [1,1], 2, 7>; // Unsupported = 1 311 312defm : SBWriteResPair<WriteCvtPH2PS, [SBPort1], 3>; 313defm : SBWriteResPair<WriteCvtPH2PSY, [SBPort1], 3>; 314defm : SBWriteResPair<WriteCvtPH2PSZ, [SBPort1], 3>; // Unsupported = 1 315 316defm : X86WriteRes<WriteCvtPS2PH, [SBPort1], 3, [1], 1>; 317defm : X86WriteRes<WriteCvtPS2PHY, [SBPort1], 3, [1], 1>; 318defm : X86WriteRes<WriteCvtPS2PHZ, [SBPort1], 3, [1], 1>; // Unsupported = 1 319defm : X86WriteRes<WriteCvtPS2PHSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; 320defm : X86WriteRes<WriteCvtPS2PHYSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; 321defm : X86WriteRes<WriteCvtPS2PHZSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; // Unsupported = 1 322 323// Vector integer operations. 324defm : X86WriteRes<WriteVecLoad, [SBPort23], 5, [1], 1>; 325defm : X86WriteRes<WriteVecLoadX, [SBPort23], 6, [1], 1>; 326defm : X86WriteRes<WriteVecLoadY, [SBPort23], 7, [1], 1>; 327defm : X86WriteRes<WriteVecLoadNT, [SBPort23], 6, [1], 1>; 328defm : X86WriteRes<WriteVecLoadNTY, [SBPort23], 7, [1], 1>; 329defm : X86WriteRes<WriteVecMaskedLoad, [SBPort23,SBPort05], 8, [1,2], 3>; 330defm : X86WriteRes<WriteVecMaskedLoadY, [SBPort23,SBPort05], 9, [1,2], 3>; 331defm : X86WriteRes<WriteVecStore, [SBPort23,SBPort4], 1, [1,1], 1>; 332defm : X86WriteRes<WriteVecStoreX, [SBPort23,SBPort4], 1, [1,1], 1>; 333defm : X86WriteRes<WriteVecStoreY, [SBPort23,SBPort4], 1, [1,1], 1>; 334defm : X86WriteRes<WriteVecStoreNT, [SBPort23,SBPort4], 1, [1,1], 1>; 335defm : X86WriteRes<WriteVecStoreNTY, [SBPort23,SBPort4], 1, [1,1], 1>; 336defm : X86WriteRes<WriteVecMaskedStore, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 337defm : X86WriteRes<WriteVecMaskedStoreY, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 338defm : X86WriteRes<WriteVecMove, [SBPort05], 1, [1], 1>; 339defm : X86WriteRes<WriteVecMoveX, [SBPort015], 1, [1], 1>; 340defm : X86WriteRes<WriteVecMoveY, [SBPort05], 1, [1], 1>; 341defm : X86WriteRes<WriteVecMoveToGpr, [SBPort0], 2, [1], 1>; 342defm : X86WriteRes<WriteVecMoveFromGpr, [SBPort5], 1, [1], 1>; 343 344defm : SBWriteResPair<WriteVecLogic, [SBPort015], 1, [1], 1, 5>; 345defm : SBWriteResPair<WriteVecLogicX,[SBPort015], 1, [1], 1, 6>; 346defm : SBWriteResPair<WriteVecLogicY,[SBPort015], 1, [1], 1, 7>; 347defm : SBWriteResPair<WriteVecLogicZ,[SBPort015], 1, [1], 1, 7>; // Unsupported = 1 348defm : SBWriteResPair<WriteVecTest, [SBPort0,SBPort5], 2, [1,1], 2, 6>; 349defm : SBWriteResPair<WriteVecTestY, [SBPort0,SBPort5], 2, [1,1], 2, 7>; 350defm : SBWriteResPair<WriteVecTestZ, [SBPort0,SBPort5], 2, [1,1], 2, 7>; // Unsupported = 1 351defm : SBWriteResPair<WriteVecALU, [SBPort1], 3, [1], 1, 5>; 352defm : SBWriteResPair<WriteVecALUX, [SBPort15], 1, [1], 1, 6>; 353defm : SBWriteResPair<WriteVecALUY, [SBPort15], 1, [1], 1, 7>; 354defm : SBWriteResPair<WriteVecALUZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1 355defm : SBWriteResPair<WriteVecIMul, [SBPort0], 5, [1], 1, 5>; 356defm : SBWriteResPair<WriteVecIMulX, [SBPort0], 5, [1], 1, 6>; 357defm : SBWriteResPair<WriteVecIMulY, [SBPort0], 5, [1], 1, 7>; 358defm : SBWriteResPair<WriteVecIMulZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 359defm : SBWriteResPair<WritePMULLD, [SBPort0], 5, [1], 1, 6>; 360defm : SBWriteResPair<WritePMULLDY, [SBPort0], 5, [1], 1, 7>; // TODO this is probably wrong for 256/512-bit for the "generic" model 361defm : SBWriteResPair<WritePMULLDZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 362defm : SBWriteResPair<WriteShuffle, [SBPort5], 1, [1], 1, 5>; 363defm : SBWriteResPair<WriteShuffleX, [SBPort15], 1, [1], 1, 6>; 364defm : SBWriteResPair<WriteShuffleY, [SBPort5], 1, [1], 1, 7>; 365defm : SBWriteResPair<WriteShuffleZ, [SBPort5], 1, [1], 1, 7>; // Unsupported = 1 366defm : SBWriteResPair<WriteVarShuffle, [SBPort15], 1, [1], 1, 5>; 367defm : SBWriteResPair<WriteVarShuffleX, [SBPort15], 1, [1], 1, 6>; 368defm : SBWriteResPair<WriteVarShuffleY, [SBPort15], 1, [1], 1, 7>; 369defm : SBWriteResPair<WriteVarShuffleZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1 370defm : SBWriteResPair<WriteBlend, [SBPort15], 1, [1], 1, 6>; 371defm : SBWriteResPair<WriteBlendY, [SBPort15], 1, [1], 1, 7>; 372defm : SBWriteResPair<WriteBlendZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1 373defm : SBWriteResPair<WriteVarBlend, [SBPort15], 2, [2], 2, 6>; 374defm : SBWriteResPair<WriteVarBlendY,[SBPort15], 2, [2], 2, 7>; 375defm : SBWriteResPair<WriteVarBlendZ,[SBPort15], 2, [2], 2, 7>; // Unsupported = 1 376defm : SBWriteResPair<WriteMPSAD, [SBPort0, SBPort15], 7, [1,2], 3, 6>; 377defm : SBWriteResPair<WriteMPSADY, [SBPort0, SBPort15], 7, [1,2], 3, 7>; 378defm : SBWriteResPair<WriteMPSADZ, [SBPort0, SBPort15], 7, [1,2], 3, 7>; // Unsupported = 1 379defm : SBWriteResPair<WritePSADBW, [SBPort0], 5, [1], 1, 5>; 380defm : SBWriteResPair<WritePSADBWX, [SBPort0], 5, [1], 1, 6>; 381defm : SBWriteResPair<WritePSADBWY, [SBPort0], 5, [1], 1, 7>; 382defm : SBWriteResPair<WritePSADBWZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 383defm : SBWriteResPair<WritePHMINPOS, [SBPort0], 5, [1], 1, 6>; 384 385// Vector integer shifts. 386defm : SBWriteResPair<WriteVecShift, [SBPort5], 1, [1], 1, 5>; 387defm : SBWriteResPair<WriteVecShiftX, [SBPort0,SBPort15], 2, [1,1], 2, 6>; 388defm : SBWriteResPair<WriteVecShiftY, [SBPort0,SBPort15], 4, [1,1], 2, 7>; 389defm : SBWriteResPair<WriteVecShiftZ, [SBPort0,SBPort15], 4, [1,1], 2, 7>; // Unsupported = 1 390defm : SBWriteResPair<WriteVecShiftImm, [SBPort5], 1, [1], 1, 5>; 391defm : SBWriteResPair<WriteVecShiftImmX, [SBPort0], 1, [1], 1, 6>; 392defm : SBWriteResPair<WriteVecShiftImmY, [SBPort0], 1, [1], 1, 7>; 393defm : SBWriteResPair<WriteVecShiftImmZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1 394defm : SBWriteResPair<WriteVarVecShift, [SBPort0], 1, [1], 1, 6>; 395defm : SBWriteResPair<WriteVarVecShiftY, [SBPort0], 1, [1], 1, 7>; 396defm : SBWriteResPair<WriteVarVecShiftZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1 397 398// Vector insert/extract operations. 399def : WriteRes<WriteVecInsert, [SBPort5,SBPort15]> { 400 let Latency = 2; 401 let NumMicroOps = 2; 402} 403def : WriteRes<WriteVecInsertLd, [SBPort23,SBPort15]> { 404 let Latency = 7; 405 let NumMicroOps = 2; 406} 407 408def : WriteRes<WriteVecExtract, [SBPort0,SBPort15]> { 409 let Latency = 3; 410 let NumMicroOps = 2; 411} 412def : WriteRes<WriteVecExtractSt, [SBPort4,SBPort23,SBPort15]> { 413 let Latency = 5; 414 let NumMicroOps = 3; 415} 416 417//////////////////////////////////////////////////////////////////////////////// 418// Horizontal add/sub instructions. 419//////////////////////////////////////////////////////////////////////////////// 420 421defm : SBWriteResPair<WriteFHAdd, [SBPort1,SBPort5], 5, [1,2], 3, 6>; 422defm : SBWriteResPair<WriteFHAddY, [SBPort1,SBPort5], 5, [1,2], 3, 7>; 423defm : SBWriteResPair<WriteFHAddZ, [SBPort1,SBPort5], 5, [1,2], 3, 7>; // Unsupported = 1 424defm : SBWriteResPair<WritePHAdd, [SBPort15], 3, [3], 3, 5>; 425defm : SBWriteResPair<WritePHAddX, [SBPort15], 3, [3], 3, 6>; 426defm : SBWriteResPair<WritePHAddY, [SBPort15], 3, [3], 3, 7>; 427defm : SBWriteResPair<WritePHAddZ, [SBPort15], 3, [3], 3, 7>; // Unsupported = 1 428 429//////////////////////////////////////////////////////////////////////////////// 430// String instructions. 431//////////////////////////////////////////////////////////////////////////////// 432 433// Packed Compare Implicit Length Strings, Return Mask 434def : WriteRes<WritePCmpIStrM, [SBPort0]> { 435 let Latency = 11; 436 let NumMicroOps = 3; 437 let ResourceCycles = [3]; 438} 439def : WriteRes<WritePCmpIStrMLd, [SBPort0, SBPort23]> { 440 let Latency = 17; 441 let NumMicroOps = 4; 442 let ResourceCycles = [3,1]; 443} 444 445// Packed Compare Explicit Length Strings, Return Mask 446def : WriteRes<WritePCmpEStrM, [SBPort015]> { 447 let Latency = 11; 448 let ResourceCycles = [8]; 449} 450def : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> { 451 let Latency = 11; 452 let ResourceCycles = [7, 1]; 453} 454 455// Packed Compare Implicit Length Strings, Return Index 456def : WriteRes<WritePCmpIStrI, [SBPort0]> { 457 let Latency = 11; 458 let NumMicroOps = 3; 459 let ResourceCycles = [3]; 460} 461def : WriteRes<WritePCmpIStrILd, [SBPort0,SBPort23]> { 462 let Latency = 17; 463 let NumMicroOps = 4; 464 let ResourceCycles = [3,1]; 465} 466 467// Packed Compare Explicit Length Strings, Return Index 468def : WriteRes<WritePCmpEStrI, [SBPort015]> { 469 let Latency = 4; 470 let ResourceCycles = [8]; 471} 472def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> { 473 let Latency = 4; 474 let ResourceCycles = [7, 1]; 475} 476 477// MOVMSK Instructions. 478def : WriteRes<WriteFMOVMSK, [SBPort0]> { let Latency = 2; } 479def : WriteRes<WriteVecMOVMSK, [SBPort0]> { let Latency = 2; } 480def : WriteRes<WriteVecMOVMSKY, [SBPort0]> { let Latency = 2; } 481def : WriteRes<WriteMMXMOVMSK, [SBPort0]> { let Latency = 1; } 482 483// AES Instructions. 484def : WriteRes<WriteAESDecEnc, [SBPort5,SBPort015]> { 485 let Latency = 7; 486 let NumMicroOps = 2; 487 let ResourceCycles = [1,1]; 488} 489def : WriteRes<WriteAESDecEncLd, [SBPort5,SBPort23,SBPort015]> { 490 let Latency = 13; 491 let NumMicroOps = 3; 492 let ResourceCycles = [1,1,1]; 493} 494 495def : WriteRes<WriteAESIMC, [SBPort5]> { 496 let Latency = 12; 497 let NumMicroOps = 2; 498 let ResourceCycles = [2]; 499} 500def : WriteRes<WriteAESIMCLd, [SBPort5,SBPort23]> { 501 let Latency = 18; 502 let NumMicroOps = 3; 503 let ResourceCycles = [2,1]; 504} 505 506def : WriteRes<WriteAESKeyGen, [SBPort015]> { 507 let Latency = 8; 508 let ResourceCycles = [11]; 509} 510def : WriteRes<WriteAESKeyGenLd, [SBPort015, SBPort23]> { 511 let Latency = 8; 512 let ResourceCycles = [10, 1]; 513} 514 515// Carry-less multiplication instructions. 516def : WriteRes<WriteCLMul, [SBPort015]> { 517 let Latency = 14; 518 let ResourceCycles = [18]; 519} 520def : WriteRes<WriteCLMulLd, [SBPort015, SBPort23]> { 521 let Latency = 14; 522 let ResourceCycles = [17, 1]; 523} 524 525// Load/store MXCSR. 526// FIXME: This is probably wrong. Only STMXCSR should require Port4. 527def : WriteRes<WriteLDMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } 528def : WriteRes<WriteSTMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } 529 530def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; } 531def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; } 532def : WriteRes<WriteFence, [SBPort23, SBPort4]>; 533def : WriteRes<WriteNop, []>; 534 535// AVX2/FMA is not supported on that architecture, but we should define the basic 536// scheduling resources anyway. 537defm : SBWriteResPair<WriteFShuffle256, [SBPort5], 1, [1], 1, 7>; 538defm : SBWriteResPair<WriteFVarShuffle256, [SBPort5], 1, [1], 1, 7>; 539defm : SBWriteResPair<WriteShuffle256, [SBPort5], 1, [1], 1, 7>; 540defm : SBWriteResPair<WriteVarShuffle256, [SBPort5], 1, [1], 1, 7>; 541defm : SBWriteResPair<WriteFMA, [SBPort01], 5>; 542defm : SBWriteResPair<WriteFMAX, [SBPort01], 5>; 543defm : SBWriteResPair<WriteFMAY, [SBPort01], 5>; 544defm : SBWriteResPair<WriteFMAZ, [SBPort01], 5>; // Unsupported = 1 545 546// Remaining SNB instrs. 547 548def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> { 549 let Latency = 1; 550 let NumMicroOps = 1; 551 let ResourceCycles = [1]; 552} 553def: InstRW<[SBWriteResGroup1], (instrs COMP_FST0r, 554 COM_FST0r, 555 UCOM_FPr, 556 UCOM_Fr)>; 557 558def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> { 559 let Latency = 1; 560 let NumMicroOps = 1; 561 let ResourceCycles = [1]; 562} 563def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP, 564 LD_Frr, ST_Frr, ST_FPrr)>; 565def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared to other Intel CPUs. 566def: InstRW<[SBWriteResGroup2], (instrs RETQ)>; 567 568def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> { 569 let Latency = 1; 570 let NumMicroOps = 1; 571 let ResourceCycles = [1]; 572} 573def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>; 574 575def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> { 576 let Latency = 1; 577 let NumMicroOps = 1; 578 let ResourceCycles = [1]; 579} 580def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABS(B|D|W)rr", 581 "MMX_PADDQirr", 582 "MMX_PALIGNRrri", 583 "MMX_PSIGN(B|D|W)rr")>; 584 585def SBWriteResGroup9 : SchedWriteRes<[SBPort05]> { 586 let Latency = 2; 587 let NumMicroOps = 2; 588 let ResourceCycles = [2]; 589} 590def: InstRW<[SBWriteResGroup9], (instregex "ROL(8|16|32|64)r1", 591 "ROL(8|16|32|64)ri", 592 "ROR(8|16|32|64)r1", 593 "ROR(8|16|32|64)ri", 594 "SET(A|BE)r")>; 595 596def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> { 597 let Latency = 2; 598 let NumMicroOps = 2; 599 let ResourceCycles = [2]; 600} 601def: InstRW<[SBWriteResGroup11], (instrs SCASB, 602 SCASL, 603 SCASQ, 604 SCASW)>; 605 606def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> { 607 let Latency = 2; 608 let NumMicroOps = 2; 609 let ResourceCycles = [1,1]; 610} 611def: InstRW<[SBWriteResGroup12], (instregex "(V?)COMISDrr", 612 "(V?)COMISSrr", 613 "(V?)UCOMISDrr", 614 "(V?)UCOMISSrr")>; 615 616def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> { 617 let Latency = 2; 618 let NumMicroOps = 2; 619 let ResourceCycles = [1,1]; 620} 621def: InstRW<[SBWriteResGroup15], (instrs CWD, 622 FNSTSW16r)>; 623 624def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> { 625 let Latency = 2; 626 let NumMicroOps = 2; 627 let ResourceCycles = [1,1]; 628} 629def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ)>; 630def: InstRW<[SBWriteResGroup18], (instregex "MMX_MOVDQ2Qrr")>; 631 632def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> { 633 let Latency = 3; 634 let NumMicroOps = 1; 635 let ResourceCycles = [1]; 636} 637def: InstRW<[SBWriteResGroup21], (instregex "PUSHFS64")>; 638 639def SBWriteResGroup21_16i : SchedWriteRes<[SBPort1, SBPort015]> { 640 let Latency = 4; 641 let NumMicroOps = 2; 642 let ResourceCycles = [1,1]; 643} 644def: InstRW<[SBWriteResGroup21_16i], (instrs IMUL16rri, IMUL16rri8)>; 645 646def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> { 647 let Latency = 3; 648 let NumMicroOps = 2; 649 let ResourceCycles = [1,1]; 650} 651def: InstRW<[SBWriteResGroup22], (instregex "(V?)EXTRACTPSrr")>; 652 653def SBWriteResGroup23_2 : SchedWriteRes<[SBPort05]> { 654 let Latency = 3; 655 let NumMicroOps = 3; 656 let ResourceCycles = [3]; 657} 658def: InstRW<[SBWriteResGroup23_2], (instregex "ROL(8|16|32|64)rCL", 659 "ROR(8|16|32|64)rCL", 660 "SAR(8|16|32|64)rCL", 661 "SHL(8|16|32|64)rCL", 662 "SHR(8|16|32|64)rCL")>; 663 664def SBWriteResGroup25 : SchedWriteRes<[SBPort015]> { 665 let Latency = 2; 666 let NumMicroOps = 3; 667 let ResourceCycles = [3]; 668} 669def: InstRW<[SBWriteResGroup25], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr, 670 XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr, 671 XCHG16ar, XCHG32ar, XCHG64ar)>; 672 673def SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> { 674 let Latency = 7; 675 let NumMicroOps = 3; 676 let ResourceCycles = [1,2]; 677} 678def: InstRW<[SBWriteResGroup25_1], (instrs LEAVE, LEAVE64)>; 679 680def SBWriteResGroup26_2 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> { 681 let Latency = 3; 682 let NumMicroOps = 3; 683 let ResourceCycles = [1,1,1]; 684} 685def: InstRW<[SBWriteResGroup26_2], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>; 686 687def SBWriteResGroup27 : SchedWriteRes<[SBPort0,SBPort1]> { 688 let Latency = 4; 689 let NumMicroOps = 2; 690 let ResourceCycles = [1,1]; 691} 692def: InstRW<[SBWriteResGroup27], (instrs IMUL64r, MUL64r)>; 693 694def SBWriteResGroup27_1 : SchedWriteRes<[SBPort1,SBPort05,SBPort015]> { 695 let Latency = 4; 696 let NumMicroOps = 3; 697 let ResourceCycles = [1,1,1]; 698} 699def: InstRW<[SBWriteResGroup27_1], (instrs IMUL32r, MUL32r)>; 700 701def SBWriteResGroup27_2 : SchedWriteRes<[SBPort1,SBPort05,SBPort015]> { 702 let Latency = 4; 703 let NumMicroOps = 4; 704 let ResourceCycles = [1,1,2]; 705} 706def: InstRW<[SBWriteResGroup27_2], (instrs IMUL16r, MUL16r)>; 707 708def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> { 709 let Latency = 4; 710 let NumMicroOps = 2; 711 let ResourceCycles = [1,1]; 712} 713def: InstRW<[SBWriteResGroup29], (instregex "MOV64sr")>; 714 715def SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> { 716 let Latency = 4; 717 let NumMicroOps = 4; 718 let ResourceCycles = [1,3]; 719} 720def: InstRW<[SBWriteResGroup29_2], (instrs PAUSE)>; 721 722def SBWriteResGroup30 : SchedWriteRes<[SBPort0]> { 723 let Latency = 5; 724 let NumMicroOps = 1; 725 let ResourceCycles = [1]; 726} 727def: InstRW<[SBWriteResGroup30], (instregex "(V?)PCMPGTQrr")>; 728 729def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> { 730 let Latency = 5; 731 let NumMicroOps = 1; 732 let ResourceCycles = [1]; 733} 734def: InstRW<[SBWriteResGroup31], (instregex "MOVSX(16|32|64)rm(8|16|32)", 735 "MOVZX(16|32|64)rm(8|16)")>; 736 737def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> { 738 let Latency = 5; 739 let NumMicroOps = 2; 740 let ResourceCycles = [1,1]; 741} 742def: InstRW<[SBWriteResGroup33], (instregex "PUSH(16r|32r|64r|64i8)")>; 743 744def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> { 745 let Latency = 5; 746 let NumMicroOps = 3; 747 let ResourceCycles = [1,2]; 748} 749def: InstRW<[SBWriteResGroup35], (instrs CLI)>; 750 751def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { 752 let Latency = 5; 753 let NumMicroOps = 3; 754 let ResourceCycles = [1,1,1]; 755} 756def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m", 757 "PUSHGS64")>; 758 759def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { 760 let Latency = 5; 761 let NumMicroOps = 3; 762 let ResourceCycles = [1,1,1]; 763} 764def: InstRW<[SBWriteResGroup36], (instrs CALL64pcrel32)>; 765def: InstRW<[SBWriteResGroup36], (instregex "CALL(16|32|64)r", 766 "(V?)EXTRACTPSmr")>; 767 768def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { 769 let Latency = 5; 770 let NumMicroOps = 3; 771 let ResourceCycles = [1,1,1]; 772} 773def: InstRW<[SBWriteResGroup40], (instrs STOSB, STOSL, STOSQ, STOSW)>; 774 775def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> { 776 let Latency = 5; 777 let NumMicroOps = 4; 778 let ResourceCycles = [1,3]; 779} 780def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>; 781 782def SBWriteResGroup42 : SchedWriteRes<[SBPort05,SBPort015]> { 783 let Latency = 5; 784 let NumMicroOps = 4; 785 let ResourceCycles = [1,3]; 786} 787def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG(8|16|32|64)rr")>; 788 789def SBWriteResGroup43 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 790 let Latency = 3; 791 let NumMicroOps = 4; 792 let ResourceCycles = [1,1,2]; 793} 794def: InstRW<[SBWriteResGroup43], (instregex "SET(A|BE)m")>; 795 796def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> { 797 let Latency = 5; 798 let NumMicroOps = 4; 799 let ResourceCycles = [1,1,1,1]; 800} 801def: InstRW<[SBWriteResGroup45], (instregex "(V?)PEXTR(D|Q)mr", 802 "PUSHF(16|64)")>; 803 804def SBWriteResGroup46 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { 805 let Latency = 5; 806 let NumMicroOps = 4; 807 let ResourceCycles = [1,1,1,1]; 808} 809def: InstRW<[SBWriteResGroup46], (instregex "CLFLUSH")>; 810 811def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { 812 let Latency = 5; 813 let NumMicroOps = 5; 814 let ResourceCycles = [1,2,1,1]; 815} 816def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>; 817 818def SBWriteResGroup48 : SchedWriteRes<[SBPort23]> { 819 let Latency = 6; 820 let NumMicroOps = 1; 821 let ResourceCycles = [1]; 822} 823def: InstRW<[SBWriteResGroup48], (instregex "MMX_MOVD64from64rm", 824 "POP(16|32|64)r", 825 "VBROADCASTSSrm", 826 "(V?)MOV64toPQIrm", 827 "(V?)MOVDDUPrm", 828 "(V?)MOVDI2PDIrm", 829 "(V?)MOVQI2PQIrm", 830 "(V?)MOVSDrm", 831 "(V?)MOVSHDUPrm", 832 "(V?)MOVSLDUPrm", 833 "(V?)MOVSSrm")>; 834 835def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> { 836 let Latency = 6; 837 let NumMicroOps = 2; 838 let ResourceCycles = [1,1]; 839} 840def: InstRW<[SBWriteResGroup49], (instregex "MOV16sm")>; 841 842def SBWriteResGroup50 : SchedWriteRes<[SBPort23,SBPort05]> { 843 let Latency = 6; 844 let NumMicroOps = 2; 845 let ResourceCycles = [1,1]; 846} 847def: InstRW<[SBWriteResGroup50], (instregex "BT(16|32|64)mi8")>; 848 849def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> { 850 let Latency = 6; 851 let NumMicroOps = 2; 852 let ResourceCycles = [1,1]; 853} 854def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABS(B|D|W)rm", 855 "MMX_PALIGNRrmi", 856 "MMX_PSIGN(B|D|W)rm")>; 857 858def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> { 859 let Latency = 6; 860 let NumMicroOps = 2; 861 let ResourceCycles = [1,1]; 862} 863def: InstRW<[SBWriteResGroup52], (instrs LODSL, LODSQ)>; 864 865def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> { 866 let Latency = 6; 867 let NumMicroOps = 3; 868 let ResourceCycles = [1,2]; 869} 870def: InstRW<[SBWriteResGroup53], (instregex "ST_F(32|64)m", 871 "ST_FP(32|64|80)m")>; 872 873def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> { 874 let Latency = 7; 875 let NumMicroOps = 1; 876 let ResourceCycles = [1]; 877} 878def: InstRW<[SBWriteResGroup54], (instregex "VBROADCASTSDYrm", 879 "VBROADCASTSSYrm", 880 "VMOVDDUPYrm", 881 "VMOVSHDUPYrm", 882 "VMOVSLDUPYrm")>; 883 884def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> { 885 let Latency = 7; 886 let NumMicroOps = 2; 887 let ResourceCycles = [1,1]; 888} 889def: InstRW<[SBWriteResGroup58], (instrs VINSERTF128rm)>; 890 891def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> { 892 let Latency = 7; 893 let NumMicroOps = 2; 894 let ResourceCycles = [1,1]; 895} 896def: InstRW<[SBWriteResGroup59], (instregex "MMX_PADDQirm")>; 897 898def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> { 899 let Latency = 7; 900 let NumMicroOps = 3; 901 let ResourceCycles = [2,1]; 902} 903def: InstRW<[SBWriteResGroup62], (instregex "VER(R|W)m")>; 904 905def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> { 906 let Latency = 7; 907 let NumMicroOps = 3; 908 let ResourceCycles = [1,2]; 909} 910def: InstRW<[SBWriteResGroup63], (instrs LODSB, LODSW)>; 911 912def SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { 913 let Latency = 7; 914 let NumMicroOps = 3; 915 let ResourceCycles = [1,1,1]; 916} 917def: InstRW<[SBWriteResGroup64], (instrs FARJMP64)>; 918 919def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> { 920 let Latency = 7; 921 let NumMicroOps = 4; 922 let ResourceCycles = [1,1,2]; 923} 924def: InstRW<[SBWriteResGroup66], (instrs FNSTSWm)>; 925 926def SBWriteResGroup67 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> { 927 let Latency = 7; 928 let NumMicroOps = 4; 929 let ResourceCycles = [1,2,1]; 930} 931def: InstRW<[SBWriteResGroup67], (instregex "SLDT(16|32|64)r", 932 "STR(16|32|64)r")>; 933 934def SBWriteResGroup68 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { 935 let Latency = 7; 936 let NumMicroOps = 4; 937 let ResourceCycles = [1,1,2]; 938} 939def: InstRW<[SBWriteResGroup68], (instrs FNSTCW16m)>; 940def: InstRW<[SBWriteResGroup68], (instregex "CALL(16|32|64)m")>; 941 942def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 943 let Latency = 7; 944 let NumMicroOps = 4; 945 let ResourceCycles = [1,2,1]; 946} 947def: InstRW<[SBWriteResGroup69], (instregex "BTC(16|32|64)mi8", 948 "BTR(16|32|64)mi8", 949 "BTS(16|32|64)mi8", 950 "SAR(8|16|32|64)m1", 951 "SAR(8|16|32|64)mi", 952 "SHL(8|16|32|64)m1", 953 "SHL(8|16|32|64)mi", 954 "SHR(8|16|32|64)m1", 955 "SHR(8|16|32|64)mi")>; 956 957def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 958 let Latency = 8; 959 let NumMicroOps = 3; 960 let ResourceCycles = [1,1,1]; 961} 962def: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>; 963 964def SBWriteResGroup81 : SchedWriteRes<[SBPort23,SBPort015]> { 965 let Latency = 8; 966 let NumMicroOps = 4; 967 let ResourceCycles = [1,3]; 968} 969def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16|32|64)rm")>; 970 971def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> { 972 let Latency = 8; 973 let NumMicroOps = 5; 974 let ResourceCycles = [2,3]; 975} 976def: InstRW<[SBWriteResGroup83], (instrs CMPSB, 977 CMPSL, 978 CMPSQ, 979 CMPSW)>; 980 981def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { 982 let Latency = 8; 983 let NumMicroOps = 5; 984 let ResourceCycles = [1,2,2]; 985} 986def: InstRW<[SBWriteResGroup84], (instrs FLDCW16m)>; 987 988def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 989 let Latency = 8; 990 let NumMicroOps = 5; 991 let ResourceCycles = [1,2,2]; 992} 993def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m1", 994 "ROL(8|16|32|64)mi", 995 "ROR(8|16|32|64)m1", 996 "ROR(8|16|32|64)mi")>; 997 998def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { 999 let Latency = 8; 1000 let NumMicroOps = 5; 1001 let ResourceCycles = [1,2,2]; 1002} 1003def: InstRW<[SBWriteResGroup86], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>; 1004def: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>; 1005 1006def SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { 1007 let Latency = 8; 1008 let NumMicroOps = 5; 1009 let ResourceCycles = [1,1,1,2]; 1010} 1011def: InstRW<[SBWriteResGroup87], (instrs FARCALL64)>; 1012 1013def SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 1014 let Latency = 9; 1015 let NumMicroOps = 3; 1016 let ResourceCycles = [1,1,1]; 1017} 1018def: InstRW<[SBWriteResGroup93], (instregex "CVT(T?)SD2SI(64)?rm", 1019 "CVT(T?)SS2SI(64)?rm")>; 1020 1021def SBWriteResGroup93_1 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 1022 let Latency = 9; 1023 let NumMicroOps = 3; 1024 let ResourceCycles = [1,1,1]; 1025} 1026def: InstRW<[SBWriteResGroup93_1], (instrs IMUL64m, MUL64m)>; 1027 1028def SBWriteResGroup93_2 : SchedWriteRes<[SBPort1,SBPort23,SBPort05,SBPort015]> { 1029 let Latency = 9; 1030 let NumMicroOps = 4; 1031 let ResourceCycles = [1,1,1,1]; 1032} 1033def: InstRW<[SBWriteResGroup93_2], (instrs IMUL32m, MUL32m)>; 1034 1035def SBWriteResGroup93_3 : SchedWriteRes<[SBPort1,SBPort05,SBPort015,SBPort23]> { 1036 let Latency = 9; 1037 let NumMicroOps = 5; 1038 let ResourceCycles = [1,1,2,1]; 1039} 1040def: InstRW<[SBWriteResGroup93_3], (instrs IMUL16m, MUL16m)>; 1041 1042def SBWriteResGroup93_4 : SchedWriteRes<[SBPort1,SBPort015,SBPort23]> { 1043 let Latency = 8; 1044 let NumMicroOps = 3; 1045 let ResourceCycles = [1,1,1]; 1046} 1047def: InstRW<[SBWriteResGroup93_4], (instrs IMUL16rmi, IMUL16rmi8)>; 1048 1049def SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { 1050 let Latency = 9; 1051 let NumMicroOps = 3; 1052 let ResourceCycles = [1,1,1]; 1053} 1054def: InstRW<[SBWriteResGroup95], (instregex "LD_F(32|64|80)m")>; 1055 1056def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { 1057 let Latency = 9; 1058 let NumMicroOps = 4; 1059 let ResourceCycles = [1,1,2]; 1060} 1061def: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m", 1062 "IST_FP(16|32|64)m")>; 1063 1064def SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 1065 let Latency = 9; 1066 let NumMicroOps = 6; 1067 let ResourceCycles = [1,2,3]; 1068} 1069def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL", 1070 "ROR(8|16|32|64)mCL", 1071 "SAR(8|16|32|64)mCL", 1072 "SHL(8|16|32|64)mCL", 1073 "SHR(8|16|32|64)mCL")>; 1074 1075def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { 1076 let Latency = 9; 1077 let NumMicroOps = 6; 1078 let ResourceCycles = [1,2,3]; 1079} 1080def: SchedAlias<WriteADCRMW, SBWriteResGroup98>; 1081 1082def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> { 1083 let Latency = 9; 1084 let NumMicroOps = 6; 1085 let ResourceCycles = [1,2,2,1]; 1086} 1087def: InstRW<[SBWriteResGroup99, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr, 1088 SBB8mr, SBB16mr, SBB32mr, SBB64mr)>; 1089 1090def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort05,SBPort015]> { 1091 let Latency = 9; 1092 let NumMicroOps = 6; 1093 let ResourceCycles = [1,1,2,1,1]; 1094} 1095def: InstRW<[SBWriteResGroup100], (instregex "BT(16|32|64)mr", 1096 "BTC(16|32|64)mr", 1097 "BTR(16|32|64)mr", 1098 "BTS(16|32|64)mr")>; 1099 1100def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> { 1101 let Latency = 10; 1102 let NumMicroOps = 2; 1103 let ResourceCycles = [1,1]; 1104} 1105def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1106 "ILD_F(16|32|64)m")>; 1107 1108def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> { 1109 let Latency = 11; 1110 let NumMicroOps = 2; 1111 let ResourceCycles = [1,1]; 1112} 1113def: InstRW<[SBWriteResGroup104], (instregex "(V?)PCMPGTQrm")>; 1114 1115def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> { 1116 let Latency = 11; 1117 let NumMicroOps = 3; 1118 let ResourceCycles = [2,1]; 1119} 1120def: InstRW<[SBWriteResGroup106], (instregex "FICOM(P?)(16|32)m")>; 1121 1122def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> { 1123 let Latency = 12; 1124 let NumMicroOps = 2; 1125 let ResourceCycles = [1,1]; 1126} 1127def: InstRW<[SBWriteResGroup111], (instregex "MUL_F(32|64)m")>; 1128 1129def SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> { 1130 let Latency = 13; 1131 let NumMicroOps = 3; 1132 let ResourceCycles = [2,1]; 1133} 1134def: InstRW<[SBWriteResGroup114], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1135 1136def SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 1137 let Latency = 15; 1138 let NumMicroOps = 3; 1139 let ResourceCycles = [1,1,1]; 1140} 1141def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI(16|32)m")>; 1142 1143def SBWriteResGroup130 : SchedWriteRes<[SBPort0,SBPort23]> { 1144 let Latency = 31; 1145 let NumMicroOps = 2; 1146 let ResourceCycles = [1,1]; 1147} 1148def: InstRW<[SBWriteResGroup130], (instregex "DIV(R?)_F(32|64)m")>; 1149 1150def SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 1151 let Latency = 34; 1152 let NumMicroOps = 3; 1153 let ResourceCycles = [1,1,1]; 1154} 1155def: InstRW<[SBWriteResGroup131], (instregex "DIV(R?)_FI(16|32)m")>; 1156 1157def: InstRW<[WriteZero], (instrs CLC)>; 1158 1159} // SchedModel 1160