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Searched refs:XOR_V (Results 1 – 21 of 21) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenMCPseudoLowering.inc953 TmpInst.setOpcode(Mips::XOR_V);
969 TmpInst.setOpcode(Mips::XOR_V);
985 TmpInst.setOpcode(Mips::XOR_V);
DMipsGenMCCodeEmitter.inc2635 UINT64_C(2019557406), // XOR_V
7435 case Mips::XOR_V: {
10361 Feature_HasStdEnc | Feature_HasMSA | 0, // XOR_V = 2622
DMipsGenAsmWriter.inc3850 268459740U, // XOR_V
6481 0U, // XOR_V
DMipsGenFastISel.inc2767 return fastEmitInst_rr(Mips::XOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
DMipsGenInstrInfo.inc2637 XOR_V = 2622,
6682 …2, 3, 1, 4, 528, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2622 = XOR_V
DMipsGenGlobalISel.inc2698 …i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (XOR_V:{ *:[v16i8] } MSA1…
2699 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V,
DMipsGenDisassemblerTables.inc5289 /* 12590 */ MCD::OPC_Decode, 190, 20, 250, 1, // Opcode: XOR_V
DMipsGenAsmMatcher.inc7656 …{ 9541 /* xor.v */, Mips::XOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Featu…
DMipsGenDAGISel.inc12638 /* 23266*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XOR_V), 0,
12641 … // Dst: (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
/external/v8/src/mips/
Dconstants-mips.h792 XOR_V = (((0U << 2) + 3) << 21), enumerator
Ddisasm-mips.cc2588 case XOR_V: in DecodeTypeMsaVec()
Dassembler-mips.cc3355 V(xor_v, XOR_V) \
Dsimulator-mips.cc5745 case XOR_V: in DecodeTypeMsaVec()
/external/v8/src/mips64/
Dconstants-mips64.h826 XOR_V = (((0U << 2) + 3) << 21), enumerator
Ddisasm-mips64.cc2902 case XOR_V: in DecodeTypeMsaVec()
Dassembler-mips64.cc3672 V(xor_v, XOR_V) \
Dsimulator-mips64.cc5969 case XOR_V: in DecodeTypeMsaVec()
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3503 def XOR_V : XOR_V_ENC, XOR_V_DESC;
3505 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3509 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3513 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3524 def XOR_V : XOR_V_ENC, XOR_V_DESC;
3526 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3530 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3534 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc1719 33577837U, // XOR_V
3433 0U, // XOR_V
DMipsGenDisassemblerTables.inc2830 /* 9840 */ MCD_OPC_Decode, 166, 13, 114, // Opcode: XOR_V