| /external/llvm/lib/Target/X86/ |
| D | X86FixupSetCC.cpp | 163 unsigned ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
168 ZeroReg); in runOnMachineFunction()
174 .addReg(ZeroReg) in runOnMachineFunction()
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| D | X86FrameLowering.cpp | 552 ZeroReg = InProlog ? (unsigned)X86::RCX in emitStackProbeInline() local
598 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg) in emitStackProbeInline()
599 .addReg(ZeroReg, RegState::Undef) in emitStackProbeInline()
600 .addReg(ZeroReg, RegState::Undef); in emitStackProbeInline()
607 .addReg(ZeroReg); in emitStackProbeInline()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86FixupSetCC.cpp | 164 unsigned ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
169 ZeroReg); in runOnMachineFunction()
175 .addReg(ZeroReg) in runOnMachineFunction()
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| D | X86FlagsCopyLowering.cpp | 991 unsigned ZeroReg = MRI->createVirtualRegister(&X86::GR32RegClass); in rewriteSetCarryExtended() local
992 BuildMI(MBB, SetPos, SetLoc, TII->get(X86::MOV32r0), ZeroReg); in rewriteSetCarryExtended()
993 ZeroReg = AdjustReg(ZeroReg); in rewriteSetCarryExtended()
1018 .addReg(ZeroReg) in rewriteSetCarryExtended()
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| D | X86FrameLowering.cpp | 589 ZeroReg = InProlog ? (unsigned)X86::RCX in emitStackProbeInline() local
649 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg) in emitStackProbeInline()
650 .addReg(ZeroReg, RegState::Undef) in emitStackProbeInline()
651 .addReg(ZeroReg, RegState::Undef); in emitStackProbeInline()
658 .addReg(ZeroReg); in emitStackProbeInline()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringX8664.cpp | 350 Variable *ZeroReg = RebasePtr; in _sandbox_mem_reference() local
369 assert(ZeroReg == Base || AbsoluteAddress || isAssignedToRspOrRbp(Base)); in _sandbox_mem_reference()
373 ZeroReg = Base; in _sandbox_mem_reference()
385 ZeroReg = Base; in _sandbox_mem_reference()
404 if (Shift == 0 && isAssignedToRspOrRbp(Index) && ZeroReg == RebasePtr) { in _sandbox_mem_reference()
405 ZeroReg = Index; in _sandbox_mem_reference()
432 if (Base != nullptr && Base != ZeroReg) in _sandbox_mem_reference()
434 if (Index != nullptr && Index != ZeroReg) in _sandbox_mem_reference()
495 Func, Mem->getType(), ZeroReg, Offset, T, Shift, in _sandbox_mem_reference()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 106 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
110 Opc = Mips::ADDu, ZeroReg = Mips::ZERO; in copyPhysReg()
138 Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64; in copyPhysReg()
158 if (ZeroReg) in copyPhysReg()
159 MIB.addReg(ZeroReg); in copyPhysReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Relocation.txt | 56 Register ZeroReg, RegisterOperand GPROpnd> {
59 def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>;
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| D | MipsSEInstrInfo.cpp | 88 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
96 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
152 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
183 if (ZeroReg) in copyPhysReg()
184 MIB.addReg(ZeroReg); in copyPhysReg()
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| D | MipsSEISelDAGToDAG.cpp | 95 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
103 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
109 ZeroReg = Mips::ZERO_64; in replaceUsesWithZeroReg()
129 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) in replaceUsesWithZeroReg()
132 MO.setReg(ZeroReg); in replaceUsesWithZeroReg()
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| D | MipsAsmPrinter.cpp | 141 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch() local
142 TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); in emitPseudoIndirectBranch()
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| D | MipsInstrInfo.td | 3068 Register ZeroReg, RegisterOperand GPROpnd> {
3075 def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>;
3077 (Addiu ZeroReg, tblockaddress:$in)>;
3078 def : MipsPat<(MipsLo tjumptable:$in), (Addiu ZeroReg, tjumptable:$in)>;
3079 def : MipsPat<(MipsLo tconstpool:$in), (Addiu ZeroReg, tconstpool:$in)>;
3081 (Addiu ZeroReg, tglobaltlsaddr:$in)>;
3082 def : MipsPat<(MipsLo texternalsym:$in), (Addiu ZeroReg, texternalsym:$in)>;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 89 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
96 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
101 ZeroReg = Mips::ZERO_64; in replaceUsesWithZeroReg()
121 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) in replaceUsesWithZeroReg()
124 MO.setReg(ZeroReg); in replaceUsesWithZeroReg()
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| D | MipsSEInstrInfo.cpp | 83 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
91 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
147 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
178 if (ZeroReg) in copyPhysReg()
179 MIB.addReg(ZeroReg); in copyPhysReg()
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| D | MipsAsmPrinter.cpp | 122 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch() local
123 TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); in emitPseudoIndirectBranch()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 2851 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
2870 if (MI->getOperand(3).getReg() != ZeroReg) in canCombine()
2880 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
2881 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
3438 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
3443 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
3450 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
3466 .addReg(ZeroReg) in genAlternativeCodeSequence()
3482 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
3486 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
[all …]
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| D | AArch64ExpandPseudoInsts.cpp | 57 unsigned ExtendImm, unsigned ZeroReg,
599 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP() argument
634 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 440 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp() local
441 putConstant(I, ZeroReg, 0); in selectCmp()
446 ZeroReg)) in selectCmp()
452 RHSReg, ZeroReg)) in selectCmp()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 3560 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
3579 if (MI->getOperand(3).getReg() != ZeroReg) in canCombine()
3589 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
3590 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
4206 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
4211 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
4218 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
4234 .addReg(ZeroReg) in genAlternativeCodeSequence()
4250 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
4254 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
[all …]
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| D | AArch64ExpandPseudoInsts.cpp | 77 unsigned ExtendImm, unsigned ZeroReg,
591 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP() argument
624 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2169 unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); in loadImmediate() local
2189 SrcReg = ZeroReg; in loadImmediate()
2211 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2236 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI); in loadImmediate()
2265 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI); in loadImmediate()
3033 unsigned ZeroReg; in expandDiv() local
3037 ZeroReg = Mips::ZERO_64; in expandDiv()
3040 ZeroReg = Mips::ZERO; in expandDiv()
3051 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDiv()
3068 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDiv()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | InstructionSelectorImpl.h | 701 int64_t ZeroReg = MatchTable[CurrentIdx++]; in executeMatchTable() local
705 OutMIs[NewInsnID].addReg(ZeroReg); in executeMatchTable()
711 << OpIdx << ", " << ZeroReg << ")\n"); in executeMatchTable()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2666 unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); in loadImmediate() local
2686 SrcReg = ZeroReg; in loadImmediate()
2708 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2732 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI); in loadImmediate()
2761 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI); in loadImmediate()
3962 unsigned ZeroReg; in expandDivRem() local
3967 ZeroReg = Mips::ZERO_64; in expandDivRem()
3971 ZeroReg = Mips::ZERO; in expandDivRem()
3995 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4002 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI); in expandDivRem()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 1263 unsigned ZeroReg; in FoldImmediate() local
1266 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in FoldImmediate()
1268 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in FoldImmediate()
1273 UseMI.getOperand(UseIdx).setReg(ZeroReg); in FoldImmediate()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 4724 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; in EmitPartwordAtomicBinary() local
4788 if (ptrA != ZeroReg) { in EmitPartwordAtomicBinary()
4818 .addReg(ZeroReg).addReg(PtrReg); in EmitPartwordAtomicBinary()
4829 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg); in EmitPartwordAtomicBinary()
5087 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; in EmitInstrWithCustomInserter() local
5120 if (ptrA != ZeroReg) { in EmitInstrWithCustomInserter()
5157 .addReg(ZeroReg).addReg(PtrReg); in EmitInstrWithCustomInserter()
5173 .addReg(ZeroReg).addReg(PtrReg); in EmitInstrWithCustomInserter()
5182 .addReg(ZeroReg).addReg(PtrReg); in EmitInstrWithCustomInserter()
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