Searched refs:__REG (Results 1 – 7 of 7) sorted by relevance
15 # define __REG(x) (*((volatile u32 *)IO_ADDRESS(x))) macro16 # define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))18 # define __REG(x) (x) macro60 #define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */61 #define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */62 #define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */65 #define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */66 #define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */67 #define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */70 #define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */[all …]
14 #define GPTCR __REG(TIMER_BASE) /* Control register */15 #define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */16 #define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */17 #define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
48 __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); in mx31_spi2_hw_init()
720 __REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22); in ll_disp3_enable()
296 #define __REG(x) (*((volatile u32 *)(x))) macro
161 192 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
534 #define __REG(x) (*((volatile u32 *)(x))) macro