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Searched refs:__raw_writel (Results 1 – 25 of 81) sorted by relevance

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/external/u-boot/board/freescale/bsc9132qds/
Dspl_minimal.c22 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); in sdram_init()
23 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); in sdram_init()
24 __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); in sdram_init()
25 __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2); in sdram_init()
26 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); in sdram_init()
28 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); in sdram_init()
29 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); in sdram_init()
30 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); in sdram_init()
31 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); in sdram_init()
32 __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); in sdram_init()
[all …]
/external/u-boot/arch/arm/mach-keystone/
Dddr3.c32 __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); in ddr3_init_ddrphy()
37 __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
39 __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); in ddr3_init_ddrphy()
40 __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET); in ddr3_init_ddrphy()
41 __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET); in ddr3_init_ddrphy()
42 __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET); in ddr3_init_ddrphy()
47 __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET); in ddr3_init_ddrphy()
49 __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET); in ddr3_init_ddrphy()
50 __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET); in ddr3_init_ddrphy()
51 __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); in ddr3_init_ddrphy()
[all …]
Dpsc.c126 __raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num)); in psc_set_state()
133 __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_state()
138 __raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD); in psc_set_state()
182 __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_disable_module()
206 __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_reset_iso()
227 __raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num)); in psc_disable_domain()
231 __raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD); in psc_disable_domain()
259 __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_module_keep_in_reset_enabled()
269 __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_module_keep_in_reset_enabled()
273 __raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD); in psc_module_keep_in_reset_enabled()
[all …]
/external/u-boot/board/freescale/bsc9131rdb/
Dspl_minimal.c25 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); in sdram_init()
26 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); in sdram_init()
28 __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); in sdram_init()
29 __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); in sdram_init()
31 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); in sdram_init()
32 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); in sdram_init()
33 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); in sdram_init()
34 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); in sdram_init()
36 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); in sdram_init()
37 __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); in sdram_init()
[all …]
/external/u-boot/drivers/video/
Dipu_disp.c68 __raw_writel(0x2, DMFC_IC_CTRL); in ipu_dmfc_init()
131 __raw_writel(dmfc_wr_chan, DMFC_WR_CHAN); in ipu_dmfc_init()
132 __raw_writel(0x202020F6, DMFC_WR_CHAN_DEF); in ipu_dmfc_init()
133 __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN); in ipu_dmfc_init()
135 __raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF); in ipu_dmfc_init()
176 __raw_writel(dmfc_gen1, DMFC_GENERAL1); in ipu_dmfc_set_wait4eot()
186 __raw_writel(reg, DI_DW_GEN(di, wave_gen)); in ipu_di_data_wave_config()
197 __raw_writel(reg, DI_DW_GEN(di, wave_gen)); in ipu_di_data_pin_config()
199 __raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set)); in ipu_di_data_pin_config()
222 __raw_writel(reg, DI_SW_GEN0(di, wave_gen)); in ipu_di_sync_config()
[all …]
Dipu_common.c165 __raw_writel(reg, clk->enable_reg); in clk_ipu_enable()
171 __raw_writel(reg, &mxc_ccm->ccdr); in clk_ipu_enable()
176 __raw_writel(reg, &mxc_ccm->clpcr); in clk_ipu_enable()
187 __raw_writel(reg, clk->enable_reg); in clk_ipu_disable()
196 __raw_writel(reg, &mxc_ccm->ccdr); in clk_ipu_disable()
201 __raw_writel(reg, &mxc_ccm->clpcr); in clk_ipu_disable()
355 __raw_writel(div, DI_BS_CLKGEN0(clk->id)); in ipu_pixel_clk_set_rate()
361 __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id)); in ipu_pixel_clk_set_rate()
374 __raw_writel(disp_gen, IPU_DISP_GEN); in ipu_pixel_clk_enable()
383 __raw_writel(disp_gen, IPU_DISP_GEN); in ipu_pixel_clk_disable()
[all …]
/external/u-boot/cmd/
Dtsi148.c83 __raw_writel(htonl(0x00000000), &dev->uregs->outbound[j].otat); in tsi148_init()
84 __raw_writel(htonl(0x00000000), &dev->uregs->inbound[j].itat); in tsi148_init()
88 __raw_writel(htonl(0x00000084), &dev->uregs->vctrl); in tsi148_init()
101 __raw_writel(htonl(0x00000000), &dev->uregs->inten); in tsi148_init()
103 __raw_writel(htonl(0x00000000), &dev->uregs->inteo); in tsi148_init()
106 __raw_writel(htonl(0x03ff3f00), &dev->uregs->intc); in tsi148_init()
108 __raw_writel(htonl(0x00000000), &dev->uregs->intm1); in tsi148_init()
109 __raw_writel(htonl(0x00000000), &dev->uregs->intm2); in tsi148_init()
114 __raw_writel(val, &dev->uregs->vstat); in tsi148_init()
157 __raw_writel(htonl(pciAddr), &dev->uregs->outbound[i].otsal); in tsi148_pci_slave_window()
[all …]
/external/u-boot/drivers/dma/
Dti-edma3.c60 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
62 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH); in qedma3_start()
69 __raw_writel(qchmap, base + EDMA3_QCHMAP(cfg->chnum)); in qedma3_start()
72 __raw_writel(1 << cfg->chnum, base + EDMA3_QSECR); in qedma3_start()
73 __raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR); in qedma3_start()
76 __raw_writel(1 << cfg->chnum, base + EDMA3_QEESR); in qedma3_start()
107 __raw_writel(opt, &rg->opt); in edma3_set_dest()
108 __raw_writel(dst, &rg->dst); in edma3_set_dest()
133 __raw_writel((src_dst_bidx & 0x0000ffff) | (bidx << 16), in edma3_set_dest_index()
135 __raw_writel((src_dst_cidx & 0x0000ffff) | (cidx << 16), in edma3_set_dest_index()
[all …]
/external/u-boot/board/mpr2/
Dmpr2.c26 __raw_writel(0x36db0400, CS2BCR); /* 4 idle cycles, normal space, 16 bit data bus */ in board_init()
27 __raw_writel(0x000003c0, CS2WCR); /* (WR:8), no ext. wait */ in board_init()
30 __raw_writel(0x00000200, CS4BCR); /* no idle cycles, normal space, 8 bit data bus */ in board_init()
31 __raw_writel(0x00100981, CS4WCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ in board_init()
34 __raw_writel(0x00000200, CS5ABCR); /* no idle cycles, normal space, 8 bit data bus */ in board_init()
35 __raw_writel(0x00100981, CS5AWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ in board_init()
38 __raw_writel(0x00000200, CS5BBCR); /* no idle cycles, normal space, 8 bit data bus */ in board_init()
39 __raw_writel(0x00100981, CS5BWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ in board_init()
42 __raw_writel(0x00000200, CS6ABCR); /* no idle cycles, normal space, 8 bit data bus */ in board_init()
43 __raw_writel(0x001009C1, CS6AWCR); /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ in board_init()
/external/u-boot/board/astro/mcf5373l/
Dmcf5373l.c41 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, in dram_init()
43 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, in dram_init()
50 __raw_writel(0x33211530, &sdp->cfg1); in dram_init()
51 __raw_writel(0x56570000, &sdp->cfg2); in dram_init()
53 __raw_writel(0xE1462C02, &sdp->ctrl); in dram_init()
56 __raw_writel(0xE1462C04, &sdp->ctrl); in dram_init()
58 __raw_writel(0xE1462C04, &sdp->ctrl); in dram_init()
60 __raw_writel(0x008D0000, &sdp->mode); in dram_init()
62 __raw_writel(0x80010000, &sdp->mode); in dram_init()
69 __raw_writel(0x71462C00, &sdp->ctrl); in dram_init()
/external/u-boot/post/cpu/mpc83xx/
Decc.c26 __raw_writel(0, &ddr->capture_address); in ecc_clear()
27 __raw_writel(0, &ddr->capture_data_hi); in ecc_clear()
28 __raw_writel(0, &ddr->capture_data_lo); in ecc_clear()
29 __raw_writel(0, &ddr->capture_ecc); in ecc_clear()
30 __raw_writel(0, &ddr->capture_attributes); in ecc_clear()
88 __raw_writel(1 << errbit, &ddr->data_err_inject_lo); in ecc_post_test()
89 __raw_writel(0, &ddr->data_err_inject_hi); in ecc_post_test()
91 __raw_writel(0, &ddr->data_err_inject_lo); in ecc_post_test()
92 __raw_writel(1<<(errbit-32), &ddr->data_err_inject_hi); in ecc_post_test()
/external/u-boot/drivers/net/
Dxilinx_emaclite.c197 __raw_writel(XEL_MDIOADDR_OP_MASK in phyread()
200 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl); in phyread()
225 __raw_writel(~XEL_MDIOADDR_OP_MASK in phywrite()
228 __raw_writel(data, &regs->mdiowr); in phywrite()
229 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl); in phywrite()
332 __raw_writel(0, &regs->tx_ping_tsr); in emaclite_start()
337 __raw_writel(ENET_ADDR_LENGTH, &regs->tx_ping_tplr); in emaclite_start()
339 __raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_ping_tsr); in emaclite_start()
347 __raw_writel(0, &regs->tx_pong_tsr); in emaclite_start()
350 __raw_writel(ENET_ADDR_LENGTH, &regs->tx_pong_tplr); in emaclite_start()
[all …]
Dcpsw.c240 #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)
244 #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
342 __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL); in cpsw_ale_read()
355 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i); in cpsw_ale_write()
357 __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL); in cpsw_ale_write()
476 __raw_writel(tmp, priv->ale_regs + ALE_CONTROL); in cpsw_ale_control()
492 __raw_writel(tmp, priv->ale_regs + offset); in cpsw_ale_port_state()
539 __raw_writel(reg, &mdio_regs->user[0].access); in cpsw_mdio_read()
557 __raw_writel(reg, &mdio_regs->user[0].access); in cpsw_mdio_write()
570 __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control); in cpsw_mdio_init()
[all …]
/external/u-boot/drivers/usb/host/
Dehci-mx5.c109 __raw_writel(v, usbother_base + in mxc_set_usbcontrol()
125 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); in mxc_set_usbcontrol()
133 __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + in mxc_set_usbcontrol()
150 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); in mxc_set_usbcontrol()
161 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); in mxc_set_usbcontrol()
186 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); in mxc_set_usbcontrol()
203 __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET); in mxc_set_usbcontrol()
254 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); in ehci_hcd_init()
/external/u-boot/arch/arm/mach-imx/
Dtimer.c71 __raw_writel(GPTCR_SWR, &cur_gpt->control); in timer_init()
74 __raw_writel(0, &cur_gpt->control); in timer_init()
92 __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT), in timer_init()
99 __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ in timer_init()
102 __raw_writel(i, &cur_gpt->control); in timer_init()
Diomux-v3.c63 __raw_writel(mux_mode, base + mux_ctrl_ofs); in imx_iomux_v3_setup_pad()
66 __raw_writel(sel_input, base + sel_input_ofs); in imx_iomux_v3_setup_pad()
70 __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl, in imx_iomux_v3_setup_pad()
74 __raw_writel(pad_ctrl, base + pad_ctrl_ofs); in imx_iomux_v3_setup_pad()
/external/u-boot/drivers/serial/
Dserial_linflexuart.c48 __raw_writel(ibr, &base->linibrr); in _linflex_serial_setbrg()
49 __raw_writel(fbr, &base->linfbrr); in _linflex_serial_setbrg()
91 __raw_writel(ctrl, &base->lincr1); in _linflex_serial_init()
95 __raw_writel(ctrl, &base->lincr1); in _linflex_serial_init()
102 __raw_writel(UARTCR_UART, &base->uartcr); in _linflex_serial_init()
108 __raw_writel(UARTCR_PC1 | UARTCR_RXEN | UARTCR_TXEN | UARTCR_PC0 in _linflex_serial_init()
113 __raw_writel(ctrl, &base->lincr1); /* end init mode */ in _linflex_serial_init()
/external/u-boot/drivers/mtd/nand/
Ddavinci_nand.c125 __raw_writel(*(u32 *)buf, nand); in nand_davinci_write_buf()
185 __raw_writel(val, &davinci_emif_regs->nandfcr); in nand_davinci_enable_hwecc()
489 __raw_writel(val, &davinci_emif_regs->nandfcr); in nand_davinci_4bit_enable_hwecc()
589 __raw_writel(((ecc16[4]) >> 6) & 0x3FF, in nand_davinci_4bit_correct_data()
593 __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0), in nand_davinci_4bit_correct_data()
597 __raw_writel((ecc16[3] >> 2) & 0x3FF, in nand_davinci_4bit_correct_data()
601 __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300), in nand_davinci_4bit_correct_data()
605 __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC), in nand_davinci_4bit_correct_data()
609 __raw_writel(((ecc16[1]) >> 4) & 0x3FF, in nand_davinci_4bit_correct_data()
613 __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0), in nand_davinci_4bit_correct_data()
[all …]
/external/u-boot/arch/arm/cpu/armv7/vf610/
Dtimer.c36 __raw_writel(0, &cur_pit->mcr); in timer_init()
38 __raw_writel(TIMER_LOAD_VAL, &cur_pit->ldval1); in timer_init()
39 __raw_writel(0, &cur_pit->tctrl1); in timer_init()
40 __raw_writel(1, &cur_pit->tctrl1); in timer_init()
/external/u-boot/arch/powerpc/cpu/mpc83xx/
Dcpu_init.c219 __raw_writel(~(RSR_RES), &im->reset.rsr); in cpu_init_f()
229 __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr); in cpu_init_f()
245 __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH, in cpu_init_f()
248 __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh); in cpu_init_f()
252 __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl); in cpu_init_f()
255 __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1); in cpu_init_f()
258 __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr); in cpu_init_f()
261 __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir); in cpu_init_f()
/external/u-boot/drivers/pci/
Dpci_msc01.c39 __raw_writel(aborts, intstat); in msc01_config_access()
42 __raw_writel((bus << MSC01_PCI_CFGADDR_BNUM_SHF) | in msc01_config_access()
50 __raw_writel(*data, cfgdata); in msc01_config_access()
57 __raw_writel(aborts, intstat); in msc01_config_access()
/external/u-boot/arch/arm/mach-imx/mx7ulp/
Diomux.c44 __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) & in mx7ulp_iomux_setup_pad()
48 __raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT), in mx7ulp_iomux_setup_pad()
52 __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) & in mx7ulp_iomux_setup_pad()
/external/u-boot/drivers/usb/gadget/
Dat91_udc.c65 __raw_writel((val), (udc)->udp_baseaddr + (reg))
164 __raw_writel(csr, creg); in read_fifo()
221 __raw_writel(csr, creg); in write_fifo()
255 __raw_writel(csr, creg); in write_fifo()
346 __raw_writel(tmp, ep->creg); in at91_ep_enable()
382 __raw_writel(0, ep->creg); in at91_ep_disable()
489 __raw_writel(tmp, ep->creg); in at91_ep_queue()
578 __raw_writel(csr, creg); in at91_ep_set_halt()
823 __raw_writel(csr, creg); in handle_ep()
835 __raw_writel(csr, creg); in handle_ep()
[all …]
/external/u-boot/drivers/memory/
Dti-aemif.c44 __raw_writel(tmp, AEMIF_NAND_CONTROL); in aemif_configure()
49 __raw_writel(tmp, AEMIF_ONENAND_CONTROL); in aemif_configure()
65 __raw_writel(tmp, AEMIF_CONFIG(cs)); in aemif_configure()
/external/u-boot/drivers/rtc/
Dimxdi.c77 __raw_writel(DSR_WEF, &data.regs->dsr); in clear_write_error()
96 __raw_writel((val), &data.regs->reg), \
137 __raw_writel(0, &data.regs->dier); in di_init()

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