Searched refs:_ri (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/lib/Target/BPF/ |
| D | BPFInstrInfo.td | 126 def _ri : JMP_RI<Opc, OpcodeStr, Cond>;
180 def _ri : ALU_RI<Opc, OpcodeStr, OpNode>;
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| /external/v8/src/compiler/s390/ |
| D | code-generator-s390.cc | 469 static inline int AssembleBinOp(Instruction* instr, _RR _rr, _RM _rm, _RI _ri) { in AssembleBinOp() argument
470 return AssembleOp<2>(instr, _rr, _rm, _ri); in AssembleBinOp()
478 #define ASSEMBLE_BIN_OP(_rr, _rm, _ri) AssembleBinOp(instr, _rr, _rm, _ri) argument
489 #define ASSEMBLE_BIN32_OP(_rr, _rm, _ri) \ argument
490 { CHECK_AND_ZERO_EXT_OUTPUT(AssembleBinOp(instr, _rr, _rm, _ri)); }
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| D | BPFInstrInfo.td | 172 def _ri : JMP_RI<Opc, OpcodeStr, Cond>;
218 def _ri : ALU_RI<BPF_ALU64, Opc,
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| /external/llvm/docs/TableGen/ |
| D | LangIntro.rst | 392 def _ri : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
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| /external/swiftshader/third_party/llvm-7.0/llvm/docs/TableGen/ |
| D | LangIntro.rst | 472 def _ri : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.td | 417 def _ri: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, i1imm:$b),
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.td | 503 def _ri: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, i1imm:$b),
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.td | 405 let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
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