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Searched refs:addImm (Results 1 – 25 of 405) sorted by relevance

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/external/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp35 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
40 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
49 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
54 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
64 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
65 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
66 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
89 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
99 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
101 .addImm(0); in lowerSubvectorStore()
[all …]
DSystemZInstrInfo.cpp175 MachineInstrBuilder(MF, Ear1MI).addImm(0); in expandLoadStackGuard()
181 MachineInstrBuilder(MF, SllgMI).addReg(Reg).addReg(0).addImm(32); in expandLoadStackGuard()
187 MachineInstrBuilder(MF, Ear2MI).addImm(1); in expandLoadStackGuard()
191 MachineInstrBuilder(MF, MI).addReg(Reg).addImm(40).addReg(0); in expandLoadStackGuard()
222 .addImm(32 - Size).addImm(128 + 31).addImm(Rotate); in emitGRX32Move()
421 .addImm(CCValid).addImm(CCMask).addMBB(TBB); in InsertBranch()
602 .addImm(CCValid) in PredicateInstruction()
603 .addImm(CCMask) in PredicateInstruction()
612 .addImm(CCValid) in PredicateInstruction()
613 .addImm(CCMask) in PredicateInstruction()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp35 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
40 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
49 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
54 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
64 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
65 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
66 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
89 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
99 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
101 .addImm(0); in lowerSubvectorStore()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp177 .addImm(ARMCC::AL) in runOnMachineFunction()
981 .addImm(ARMCC::AL) in EmitJumpTableInsts()
1245 .addImm(MI->getOperand(2).getImm()) in EmitInstruction()
1261 .addImm(MI->getOperand(2).getImm()) in EmitInstruction()
1272 .addImm(ARMCC::AL) in EmitInstruction()
1309 .addImm(ARMCC::AL).addReg(0) in EmitInstruction()
1318 .addImm(ARMCC::AL) in EmitInstruction()
1327 .addImm(ARMCC::AL) in EmitInstruction()
1338 .addImm(ARMCC::AL) in EmitInstruction()
1351 .addImm(ARMCC::AL) in EmitInstruction()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCFrameLowering.cpp138 .addImm(UsedRegMask); in HandleVRSaveUpdate()
142 .addImm(UsedRegMask); in HandleVRSaveUpdate()
147 .addImm(UsedRegMask >> 16); in HandleVRSaveUpdate()
151 .addImm(UsedRegMask >> 16); in HandleVRSaveUpdate()
156 .addImm(UsedRegMask >> 16); in HandleVRSaveUpdate()
160 .addImm(UsedRegMask >> 16); in HandleVRSaveUpdate()
164 .addImm(UsedRegMask & 0xFFFF); in HandleVRSaveUpdate()
318 .addImm(FPOffset/4) in emitPrologue()
324 .addImm(LROffset / 4) in emitPrologue()
333 .addImm(FPOffset) in emitPrologue()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600ControlFlowFinalizer.cpp355 .addImm(0) // ADDR in MakeFetchClause()
356 .addImm(AluInstCount - 1); // COUNT in MakeFetchClause()
404 .addImm(LiteralPair0) in insertLiterals()
405 .addImm(LiteralPair1); in insertLiterals()
447 MILit.addImm(Literals[i]->getImm()); in MakeALUClause()
454 MILit.addImm(Literals[i + 1]->getImm()); in MakeALUClause()
460 MILit.addImm(0); in MakeALUClause()
474 BuildMI(BB, DL, TII->get(R600::FETCH_CLAUSE)).addImm(CfCount); in EmitFetchClause()
486 BuildMI(BB, DL, TII->get(R600::ALU_CLAUSE)).addImm(CfCount); in EmitALUClause()
556 .addImm(CfCount + 1) in runOnMachineFunction()
[all …]
DAMDGPUInstructionSelector.cpp151 .addImm(AMDGPU::sub0) in selectG_ADD()
153 .addImm(AMDGPU::sub1); in selectG_ADD()
225 .addImm(Tgt) in buildEXP()
230 .addImm(VM) in buildEXP()
231 .addImm(Compr) in buildEXP()
232 .addImm(Enabled); in buildEXP()
309 .addImm(0) // offset in selectG_STORE()
310 .addImm(0) // glc in selectG_STORE()
311 .addImm(0); // slc in selectG_STORE()
367 .addImm(Imm.trunc(32).getZExtValue()); in selectG_CONSTANT()
[all …]
DR600EmitClauseMarkers.cpp298 .addImm(Address++) // ADDR in MakeALUClause()
299 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].first) // KB0 in MakeALUClause()
300 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].first) // KB1 in MakeALUClause()
301 .addImm(KCacheBanks.empty()?0:2) // KM0 in MakeALUClause()
302 .addImm((KCacheBanks.size() < 2)?0:2) // KM1 in MakeALUClause()
303 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].second) // KLINE0 in MakeALUClause()
304 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].second) // KLINE1 in MakeALUClause()
305 .addImm(AluInstCount) // COUNT in MakeALUClause()
306 .addImm(1); // Enabled in MakeALUClause()
/external/llvm/lib/Target/AMDGPU/
DR600ControlFlowFinalizer.cpp339 .addImm(0) // ADDR in MakeFetchClause()
340 .addImm(AluInstCount - 1); // COUNT in MakeFetchClause()
388 .addImm(LiteralPair0) in insertLiterals()
389 .addImm(LiteralPair1); in insertLiterals()
431 MILit.addImm(Literals[i]->getImm()); in MakeALUClause()
438 MILit.addImm(Literals[i + 1]->getImm()); in MakeALUClause()
444 MILit.addImm(0); in MakeALUClause()
459 .addImm(CfCount); in EmitFetchClause()
473 .addImm(CfCount); in EmitALUClause()
541 .addImm(CfCount + 1) in runOnMachineFunction()
[all …]
DR600ISelLowering.cpp307 .addImm(isEOP(I)); // Set End of program bit in EmitInstrWithCustomInserter()
315 .addImm(isEOP(I)); // Set End of program bit in EmitInstrWithCustomInserter()
360 .addImm(SrcX) in EmitInstrWithCustomInserter()
361 .addImm(SrcY) in EmitInstrWithCustomInserter()
362 .addImm(SrcZ) in EmitInstrWithCustomInserter()
363 .addImm(SrcW) in EmitInstrWithCustomInserter()
364 .addImm(0) in EmitInstrWithCustomInserter()
365 .addImm(0) in EmitInstrWithCustomInserter()
366 .addImm(0) in EmitInstrWithCustomInserter()
367 .addImm(0) in EmitInstrWithCustomInserter()
[all …]
DR600EmitClauseMarkers.cpp283 .addImm(Address++) // ADDR in MakeALUClause()
284 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].first) // KB0 in MakeALUClause()
285 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].first) // KB1 in MakeALUClause()
286 .addImm(KCacheBanks.empty()?0:2) // KM0 in MakeALUClause()
287 .addImm((KCacheBanks.size() < 2)?0:2) // KM1 in MakeALUClause()
288 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].second) // KLINE0 in MakeALUClause()
289 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].second) // KLINE1 in MakeALUClause()
290 .addImm(AluInstCount) // COUNT in MakeALUClause()
291 .addImm(1); // Enabled in MakeALUClause()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrBuilder.h94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
100 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
134 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
138 MIB.addImm(AM.Disp); in addFullAddress()
178 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrBuilder.h128 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
145 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
150 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
168 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
169 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
184 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
188 MIB.addImm(AM.Disp); in addFullAddress()
227 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaFrameLowering.cpp57 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R27).addImm(++curgpdist); in emitPrologue()
59 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R29).addImm(curgpdist); in emitPrologue()
82 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) in emitPrologue()
86 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); in emitPrologue()
88 .addImm(getLower16(NumBytes)).addReg(Alpha::R30); in emitPrologue()
96 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); in emitPrologue()
127 .addImm(0).addReg(Alpha::R15); in emitEpilogue()
132 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) in emitEpilogue()
136 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); in emitEpilogue()
138 .addImm(getLower16(NumBytes)).addReg(Alpha::R30); in emitEpilogue()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/
DBPFInstrInfo.cpp81 .addImm(I * Alignment); in expandMEMCPY()
84 .addImm(I * Alignment); in expandMEMCPY()
94 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
96 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
101 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
103 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
108 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
110 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
138 .addImm(0); in storeRegToStackSlot()
143 .addImm(0); in storeRegToStackSlot()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h122 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
128 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
146 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
147 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
162 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
166 MIB.addImm(AM.Disp); in addFullAddress()
205 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
/external/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp164 .addImm(ARMCC::AL) in runOnMachineFunction()
1074 .addImm(ARMCC::AL) in EmitJumpTableInsts()
1314 .addImm(MI->getOperand(2).getImm()) in EmitInstruction()
1330 .addImm(MI->getOperand(2).getImm()) in EmitInstruction()
1341 .addImm(ARMCC::AL) in EmitInstruction()
1377 .addImm(ARMCC::AL).addReg(0) in EmitInstruction()
1386 .addImm(ARMCC::AL) in EmitInstruction()
1395 .addImm(ARMCC::AL) in EmitInstruction()
1406 .addImm(ARMCC::AL) in EmitInstruction()
1419 .addImm(ARMCC::AL) in EmitInstruction()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUFrameLowering.cpp124 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16) in emitPrologue()
128 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize) in emitPrologue()
132 .addImm(FrameSize); in emitPrologue()
137 .addImm(-16) in emitPrologue()
140 .addImm(FrameSize); in emitPrologue()
149 .addImm(16); in emitPrologue()
209 .addImm(FrameSize + LinkSlotOffset) in emitEpilogue()
213 .addImm(FrameSize); in emitEpilogue()
218 .addImm(16) in emitEpilogue()
221 .addImm(FrameSize); in emitEpilogue()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/X86/
DTarget.cpp116 return {llvm::MCInstBuilder(llvm::X86::MOV8ri).addReg(Reg).addImm(1)}; in setRegToConstant()
118 return {llvm::MCInstBuilder(llvm::X86::MOV16ri).addReg(Reg).addImm(1)}; in setRegToConstant()
120 return {llvm::MCInstBuilder(llvm::X86::MOV32ri).addReg(Reg).addImm(1)}; in setRegToConstant()
122 return {llvm::MCInstBuilder(llvm::X86::MOV64ri32).addReg(Reg).addImm(1)}; in setRegToConstant()
202 .addImm(Bytes); in allocateStackSpace()
211 .addImm(1) // ScaleAmt in fillStackSpace()
213 .addImm(OffsetBytes) // Disp in fillStackSpace()
216 .addImm(Imm); in fillStackSpace()
225 .addImm(1) // ScaleAmt in loadToReg()
227 .addImm(0) // Disp in loadToReg()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64ExpandPseudoInsts.cpp161 .addImm(Encoding); in tryToreplicateChunks()
182 .addImm(Imm16) in tryToreplicateChunks()
183 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt)); in tryToreplicateChunks()
206 .addImm(Imm16) in tryToreplicateChunks()
207 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt)); in tryToreplicateChunks()
343 .addImm(Encoding); in trySequenceOfOnes()
355 .addImm(getChunk(UImm, FirstMovkIdx)) in trySequenceOfOnes()
356 .addImm( in trySequenceOfOnes()
371 .addImm(getChunk(UImm, SecondMovkIdx)) in trySequenceOfOnes()
372 .addImm( in trySequenceOfOnes()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiFrameLowering.cpp81 .addImm(MaxCallFrameSize); in replaceAdjDynAllocPseudo()
117 .addImm(-4) in emitPrologue()
118 .addImm(LPAC::makePreOp(LPAC::ADD)) in emitPrologue()
125 .addImm(8) in emitPrologue()
133 .addImm(StackSize) in emitPrologue()
189 .addImm(0); in emitEpilogue()
194 .addImm(-8) in emitEpilogue()
195 .addImm(LPAC::ADD); in emitEpilogue()
/external/llvm/lib/Target/Lanai/
DLanaiFrameLowering.cpp81 .addImm(MaxCallFrameSize); in replaceAdjDynAllocPseudo()
117 .addImm(-4) in emitPrologue()
118 .addImm(LPAC::makePreOp(LPAC::ADD)) in emitPrologue()
125 .addImm(8) in emitPrologue()
133 .addImm(StackSize) in emitPrologue()
189 .addImm(0); in emitEpilogue()
194 .addImm(-8) in emitEpilogue()
195 .addImm(LPAC::ADD); in emitEpilogue()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp371 .addImm(UsedRegMask); in HandleVRSaveUpdate()
375 .addImm(UsedRegMask); in HandleVRSaveUpdate()
380 .addImm(UsedRegMask >> 16); in HandleVRSaveUpdate()
384 .addImm(UsedRegMask >> 16); in HandleVRSaveUpdate()
389 .addImm(UsedRegMask >> 16); in HandleVRSaveUpdate()
393 .addImm(UsedRegMask >> 16); in HandleVRSaveUpdate()
397 .addImm(UsedRegMask & 0xFFFF); in HandleVRSaveUpdate()
865 .addImm(8) in emitPrologue()
894 .addImm(FPOffset) in emitPrologue()
899 .addImm(PBPOffset) in emitPrologue()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinInstrInfo.cpp113 .addImm(0); in copyPhysReg()
121 BuildMI(MBB, I, DL, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0); in copyPhysReg()
134 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(0); in copyPhysReg()
183 .addImm(0); in storeRegToStackSlot()
191 .addImm(0); in storeRegToStackSlot()
199 .addImm(0); in storeRegToStackSlot()
228 .addImm(0); in loadRegFromStackSlot()
235 .addImm(0); in loadRegFromStackSlot()
242 .addImm(0); in loadRegFromStackSlot()
/external/llvm/lib/Target/PowerPC/
DPPCBranchSelector.cpp202 .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2); in runOnMachineFunction()
205 BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2); in runOnMachineFunction()
208 BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2); in runOnMachineFunction()
210 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2); in runOnMachineFunction()
212 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2); in runOnMachineFunction()
214 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2); in runOnMachineFunction()
216 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2); in runOnMachineFunction()

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