/external/llvm/test/CodeGen/SystemZ/ |
D | args-06.ll | 18 %adde = add i8 %addd, %e 19 %addf = add i8 %adde, %f 36 %adde = add i16 %addd, %e 37 %addf = add i16 %adde, %f 54 %adde = add i32 %addd, %e 55 %addf = add i32 %adde, %f 72 %adde = add i64 %addd, %e 73 %addf = add i64 %adde, %f
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
D | args-06.ll | 18 %adde = add i8 %addd, %e 19 %addf = add i8 %adde, %f 36 %adde = add i16 %addd, %e 37 %addf = add i16 %adde, %f 54 %adde = add i32 %addd, %e 55 %addf = add i32 %adde, %f 72 %adde = add i64 %addd, %e 73 %addf = add i64 %adde, %f
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
D | combine-cond-add-sub.ll | 80 %adde = add i32 %v, %ext 81 %add2 = add i32 %adde, %a 103 %adde = add i32 %add, %ext 104 store i32 %adde, i32 addrspace(1)* %gep, align 4 124 %adde = add i32 %v, %ext 125 %sub = sub i32 %adde, %a 147 %adde = add i32 %sub, %ext 148 store i32 %adde, i32 addrspace(1)* %gep, align 4
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
D | testComparesiltsll.ll | 18 ; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] 34 ; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] 63 ; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] 80 ; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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D | testComparesllltsll.ll | 18 ; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] 34 ; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] 63 ; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] 80 ; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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D | testComparesigtsll.ll | 17 ; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] 33 ; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] 77 ; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] 94 ; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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D | testComparesllgesll.ll | 16 ; CHECK-NEXT: adde r3, r5, r6 30 ; CHECK-NEXT: adde r3, r5, r6 69 ; CHECK: adde r3, r6, r3 87 ; CHECK-NEXT: adde r3, r6, r3
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D | testComparesllgtsll.ll | 17 ; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] 33 ; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] 77 ; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] 94 ; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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D | testComparesigesll.ll | 16 ; CHECK-NEXT: adde r3, r5, r6 30 ; CHECK-NEXT: adde r3, r5, r6 69 ; CHECK: adde r3, r6, r3 87 ; CHECK-NEXT: adde r3, r6, r3
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D | testCompareslllesll.ll | 17 ; CHECK-NEXT: adde r3, r5, r6 32 ; CHECK-NEXT: adde r3, r5, r6 78 ; CHECK-NEXT: adde r3, r6, r3 97 ; CHECK-NEXT: adde r3, r6, r3
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D | testComparesilesll.ll | 16 ; CHECK-NEXT: adde r3, r5, r6 30 ; CHECK-NEXT: adde r3, r5, r6 73 ; CHECK-NEXT: adde r3, r6, r3 91 ; CHECK-NEXT: adde r3, r6, r3
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D | ppc64-i128-abi.ll | 160 ; Add the upper 64-bits using adde on registers 4 and 6 168 ; Add the upper 64-bits using adde on registers 3 and 5 175 ; CHECK-LE-NEXT: adde 4, 4, 6 180 ; CHECK-BE-NEXT: adde 3, 3, 5 185 ; CHECK-LE-NOVSX-NEXT: adde 4, 4, 6 190 ; CHECK-BE-NOVSX-NEXT: adde 3, 3, 5
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D | big-endian-actual-args.ll | 4 ; RUN: grep "adde 3, 3, 5"
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D | addc.ll | 10 ; CHECK: adde r3, r5, r3
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/external/capstone/suite/MC/PowerPC/ |
D | ppc64-encoding.s.cs | 81 0x7c,0x43,0x21,0x14 = adde 2, 3, 4 82 0x7c,0x43,0x21,0x15 = adde. 2, 3, 4
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/external/llvm/test/CodeGen/PowerPC/ |
D | ppc64-i128-abi.ll | 124 ; Add the upper 64-bits using adde on registers 4 and 6 132 ; Add the upper 64-bits using adde on registers 3 and 5 139 ; CHECK-LE-NEXT: adde 4, 4, 6 144 ; CHECK-BE-NEXT: adde 3, 3, 5 149 ; CHECK-LE-NOVSX-NEXT: adde 4, 4, 6 154 ; CHECK-BE-NOVSX-NEXT: adde 3, 3, 5
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D | big-endian-actual-args.ll | 4 ; RUN: grep "adde 3, 3, 5"
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D | addc.ll | 10 ; CHECK: adde r3, r5, r3
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/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/ |
D | big-endian-actual-args.ll | 4 ; RUN: grep {adde 3, 3, 5}
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D | addc.ll | 10 ; CHECK: adde r3, r5, r3
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
D | 2011-08-29-SchedCycle.ll | 30 ; fix subc / sube (and addc / adde) to use physical register dependency instead.
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/external/llvm/test/CodeGen/ARM/ |
D | 2011-08-29-SchedCycle.ll | 30 ; fix subc / sube (and addc / adde) to use physical register dependency instead.
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/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
D | 2011-08-29-SchedCycle.ll | 30 ; fix subc / sube (and addc / adde) to use physical register dependency instead.
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/external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
D | MSP430InstrInfo.td | 434 [(set GR8:$dst, (adde GR8:$src, GR8:$src2)), 439 [(set GR16:$dst, (adde GR16:$src, GR16:$src2)), 446 [(set GR8:$dst, (adde GR8:$src, imm:$src2)), 451 [(set GR16:$dst, (adde GR16:$src, imm:$src2)), 457 [(set GR8:$dst, (adde GR8:$src, (load addr:$src2))), 462 [(set GR16:$dst, (adde GR16:$src, (load addr:$src2))), 469 [(store (adde (load addr:$dst), GR8:$src), addr:$dst), 474 [(store (adde (load addr:$dst), GR16:$src), addr:$dst), 480 [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst), 485 [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst), [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
D | MSP430InstrInfo.td | 442 [(set GR8:$dst, (adde GR8:$src, GR8:$src2)), 447 [(set GR16:$dst, (adde GR16:$src, GR16:$src2)), 454 [(set GR8:$dst, (adde GR8:$src, imm:$src2)), 459 [(set GR16:$dst, (adde GR16:$src, imm:$src2)), 465 [(set GR8:$dst, (adde GR8:$src, (load addr:$src2))), 470 [(set GR16:$dst, (adde GR16:$src, (load addr:$src2))), 477 [(store (adde (load addr:$dst), GR8:$src), addr:$dst), 482 [(store (adde (load addr:$dst), GR16:$src), addr:$dst), 488 [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst), 493 [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst), [all …]
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