1; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 2; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 3; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 5; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 6; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 7; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 8@glob = common local_unnamed_addr global i64 0, align 8 9 10define signext i32 @test_igesll(i64 %a, i64 %b) { 11; CHECK-LABEL: test_igesll: 12; CHECK: # %bb.0: # %entry 13; CHECK-NEXT: sradi r5, r3, 63 14; CHECK-NEXT: rldicl r6, r4, 1, 63 15; CHECK-NEXT: subfc r3, r4, r3 16; CHECK-NEXT: adde r3, r5, r6 17; CHECK-NEXT: blr 18entry: 19 %cmp = icmp sge i64 %a, %b 20 %conv = zext i1 %cmp to i32 21 ret i32 %conv 22} 23 24define signext i32 @test_igesll_sext(i64 %a, i64 %b) { 25; CHECK-LABEL: test_igesll_sext: 26; CHECK: # %bb.0: # %entry 27; CHECK-NEXT: sradi r5, r3, 63 28; CHECK-NEXT: rldicl r6, r4, 1, 63 29; CHECK-NEXT: subfc r3, r4, r3 30; CHECK-NEXT: adde r3, r5, r6 31; CHECK-NEXT: neg r3, r3 32; CHECK-NEXT: blr 33entry: 34 %cmp = icmp sge i64 %a, %b 35 %sub = sext i1 %cmp to i32 36 ret i32 %sub 37} 38 39define signext i32 @test_igesll_z(i64 %a) { 40; CHECK-LABEL: test_igesll_z: 41; CHECK: # %bb.0: # %entry 42; CHECK-NEXT: rldicl r3, r3, 1, 63 43; CHECK-NEXT: xori r3, r3, 1 44; CHECK-NEXT: blr 45entry: 46 %cmp = icmp sgt i64 %a, -1 47 %conv = zext i1 %cmp to i32 48 ret i32 %conv 49} 50 51define signext i32 @test_igesll_sext_z(i64 %a) { 52; CHECK-LABEL: test_igesll_sext_z: 53; CHECK: # %bb.0: # %entry 54; CHECK-NEXT: sradi r3, r3, 63 55; CHECK-NEXT: not r3, r3 56; CHECK-NEXT: blr 57entry: 58 %cmp = icmp sgt i64 %a, -1 59 %sub = sext i1 %cmp to i32 60 ret i32 %sub 61} 62 63define void @test_igesll_store(i64 %a, i64 %b) { 64; CHECK-LABEL: test_igesll_store: 65; CHECK: # %bb.0: # %entry 66; CHECK: sradi r6, r3, 63 67; CHECK: subfc r3, r4, r3 68; CHECK: rldicl r3, r4, 1, 63 69; CHECK: adde r3, r6, r3 70; CHECK: std r3 71; CHECK-NEXT: blr 72entry: 73 %cmp = icmp sge i64 %a, %b 74 %conv1 = zext i1 %cmp to i64 75 store i64 %conv1, i64* @glob, align 8 76 ret void 77} 78 79define void @test_igesll_sext_store(i64 %a, i64 %b) { 80; CHECK-LABEL: test_igesll_sext_store: 81; CHECK: # %bb.0: # %entry 82; CHECK-NEXT: sradi r6, r3, 63 83; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 84; CHECK-NEXT: subfc r3, r4, r3 85; CHECK-NEXT: rldicl r3, r4, 1, 63 86; CHECK-NEXT: ld r4, .LC0@toc@l(r5) 87; CHECK-NEXT: adde r3, r6, r3 88; CHECK-NEXT: neg r3, r3 89; CHECK-NEXT: std r3, 0(r4) 90; CHECK-NEXT: blr 91entry: 92 %cmp = icmp sge i64 %a, %b 93 %conv1 = sext i1 %cmp to i64 94 store i64 %conv1, i64* @glob, align 8 95 ret void 96} 97 98define void @test_igesll_z_store(i64 %a) { 99; CHECK-LABEL: test_igesll_z_store: 100; CHECK: # %bb.0: # %entry 101; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 102; CHECK-NEXT: not r3, r3 103; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 104; CHECK-NEXT: rldicl r3, r3, 1, 63 105; CHECK-NEXT: std r3, 0(r4) 106; CHECK-NEXT: blr 107entry: 108 %cmp = icmp sgt i64 %a, -1 109 %conv1 = zext i1 %cmp to i64 110 store i64 %conv1, i64* @glob, align 8 111 ret void 112} 113 114define void @test_igesll_sext_z_store(i64 %a) { 115; CHECK-LABEL: test_igesll_sext_z_store: 116; CHECK: # %bb.0: # %entry 117; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 118; CHECK-NEXT: not r3, r3 119; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 120; CHECK-NEXT: sradi r3, r3, 63 121; CHECK-NEXT: std r3, 122; CHECK-NEXT: blr 123entry: 124 %cmp = icmp sgt i64 %a, -1 125 %conv1 = sext i1 %cmp to i64 126 store i64 %conv1, i64* @glob, align 8 127 ret void 128} 129