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Searched refs:altera (Results 1 – 25 of 30) sorted by relevance

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/external/u-boot/board/altera/arria5-socdk/
DMAINTAINERS3 M: Chin-Liang See <clsee@altera.com>
5 F: board/altera/arria5-socdk/
/external/u-boot/board/altera/arria10-socdk/
DMAINTAINERS3 M: Chin-Liang See <clsee@altera.com>
5 F: board/altera/arria10-socdk/
DKconfig10 default "altera"
/external/u-boot/board/altera/cyclone5-socdk/
DMAINTAINERS3 M: Chin-Liang See <clsee@altera.com>
5 F: board/altera/cyclone5-socdk/
/external/u-boot/arch/arm/mach-socfpga/
DKconfig93 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
94 default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
95 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dclock_manager_gen5.c150 writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk); in cm_basic_init()
365 reg = readl(&clock_manager_base->altera.mpuclk); in cm_get_mpu_clk_hz()
416 reg = readl(&clock_manager_base->altera.mainclk); in cm_get_l4_sp_clk_hz()
Dclock_manager_arria10.c979 reg = readl(&clock_manager_base->altera.mpuclk); in cm_get_mpu_clk_hz()
/external/u-boot/drivers/ddr/
DKconfig1 source "drivers/ddr/altera/Kconfig"
/external/u-boot/arch/arm/dts/
Dsocfpga_cyclone5.dtsi3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
Dsocfpga_arria5.dtsi3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
Dsocfpga_arria10_socdk_sdmmc.dts2 * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
Dsocfpga_arria5_socdk.dts3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
Dsocfpga_cyclone5_is1.dts3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
Dsocfpga_cyclone5_socdk.dts3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
Dsocfpga_arria10_socdk.dtsi2 * Copyright (C) 2015 Altera Corporation <www.altera.com>
Dsocfpga.dtsi3 * Copyright (C) 2012 Altera <www.altera.com>
/external/u-boot/drivers/fpga/
DMakefile15 obj-y += altera.o
/external/u-boot/configs/
Dsocfpga_cyclone5_defconfig70 CONFIG_USB_GADGET_MANUFACTURER="altera"
Dsocfpga_arria5_defconfig69 CONFIG_USB_GADGET_MANUFACTURER="altera"
/external/u-boot/arch/arm/mach-socfpga/include/mach/
Dclock_manager_arria10.h89 struct socfpga_clock_manager_altera altera; member
Dclock_manager_gen5.h110 struct socfpga_clock_manager_altera altera; member
/external/u-boot/drivers/
DMakefile28 obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
/external/u-boot/doc/
DREADME.nios25 https://www.altera.com/products/processors/overview.html
DREADME.socfpga7 www.altera.com.
/external/selinux/policycoreutils/po/
Dpt_BR.po2052 "A alteração do tipo de política poderá causar o rerotulamento de todo "
2065 "A alteração ao SELinux para desativado requer a reinicialização. Isto não é "
2078 "A alteração do tipo de política poderá causar o rerotulamento de todo "
3232 "configuração do modo de reforço e alteração dos valores booleanos. Determine "
3233 "isto para verdadeiro e reinicie a máquina para que as alterações façam "
5397 "A alteração ao SELinux para desativado requer a reinicialização. Isto não é "

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