| /external/u-boot/arch/arm/mach-sunxi/ |
| D | clock_sun4i.c | 121 int axi, ahb, apb0; in clock_set_pll1() local
134 axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ in clock_set_pll1()
135 ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */ in clock_set_pll1()
138 printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); in clock_set_pll1()
141 axi = axi - 1; in clock_set_pll1()
162 writel(axi << AXI_DIV_SHIFT | in clock_set_pll1()
173 writel(axi << AXI_DIV_SHIFT | in clock_set_pll1()
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| /external/u-boot/drivers/pci/ |
| D | pci_tegra.c | 803 unsigned long fpci, axi, size; local
810 axi = pcie->cs.start;
812 afi_writel(pcie, axi, AFI_AXI_BAR0_START);
823 axi = io->phys_start;
825 afi_writel(pcie, axi, AFI_AXI_BAR1_START);
832 axi = pref->phys_start;
834 afi_writel(pcie, axi, AFI_AXI_BAR2_START);
841 axi = mem->phys_start;
843 afi_writel(pcie, axi, AFI_AXI_BAR3_START);
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| /external/u-boot/arch/mips/dts/ |
| D | img,boston.dts | 49 compatible = "xlnx,axi-pcie-host-1.00.a";
78 compatible = "xlnx,axi-pcie-host-1.00.a";
106 compatible = "xlnx,axi-pcie-host-1.00.a";
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| D | nexys4ddr.dts | 36 xlnx,s-axi-id-width = <0x1>;
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| /external/u-boot/arch/arm/dts/ |
| D | sun5i.dtsi | 191 axi: axi@01c20054 { label
193 compatible = "allwinner,sun4i-a10-axi-clk";
196 clock-output-names = "axi";
203 clocks = <&axi>, <&cpu>, <&pll6 1>;
231 compatible = "allwinner,sun4i-a10-axi-gates-clk";
233 clocks = <&axi>;
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| D | sun5i-gr8.dtsi | 191 axi: axi@01c20054 { label
193 compatible = "allwinner,sun4i-a10-axi-clk";
196 clock-output-names = "axi";
203 clocks = <&axi>, <&cpu>, <&pll6 1>;
233 clocks = <&axi>;
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| D | sun4i-a10.dtsi | 291 axi: axi@01c20054 { label
293 compatible = "allwinner,sun4i-a10-axi-clk";
296 clock-output-names = "axi";
301 compatible = "allwinner,sun4i-a10-axi-gates-clk";
303 clocks = <&axi>;
312 clocks = <&axi>;
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| D | socfpga_arria10.dtsi | 410 socfpga_axi_setup: stmmac-axi-config {
432 snps,axi-config = <&socfpga_axi_setup>;
452 snps,axi-config = <&socfpga_axi_setup>;
470 snps,axi-config = <&socfpga_axi_setup>;
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| D | imx6sx.dtsi | 1120 clock-names = "disp-axi", "csi_mclk", "dcic";
1129 clock-names = "pxp-axi", "disp-axi";
1139 clock-names = "disp-axi", "csi_mclk", "dcic";
1150 clock-names = "pix", "axi", "disp_axi";
1161 clock-names = "pix", "axi", "disp_axi";
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| D | sun6i-a31.dtsi | 226 axi: axi@01c20050 { label
228 compatible = "allwinner,sun4i-a10-axi-clk";
231 clock-output-names = "axi";
238 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
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| D | sun7i-a20.dtsi | 301 axi: axi@01c20054 { label
303 compatible = "allwinner,sun4i-a10-axi-clk";
306 clock-output-names = "axi";
313 clocks = <&axi>, <&pll6 3>, <&pll6 1>;
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| D | imx6sll.dtsi | 627 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
670 clock-names = "pix", "axi", "disp_axi";
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| D | fsl-imx8mq.dtsi | 234 clock-names = "pix", "axi", "disp_axi";
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| D | imx6ull.dtsi | 991 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
1002 clock-names = "pix", "axi", "disp_axi";
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| D | rk3399.dtsi | 184 reg-names = "axi-base", "apb-base";
1412 reset-names = "axi", "ahb", "dclk";
1438 reset-names = "axi", "ahb", "dclk";
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| D | rk3288.dtsi | 669 reset-names = "axi", "ahb", "dclk";
713 reset-names = "axi", "ahb", "dclk";
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| D | imx7ulp.dtsi | 469 clock-names = "axi", "pix", "disp_axi";
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| D | imx6sl.dtsi | 741 clock-names = "pix", "axi", "disp_axi";
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| D | dra7.dtsi | 285 axi@0 {
341 axi@1 {
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| D | imx6ul.dtsi | 862 clock-names = "pix", "axi", "disp_axi";
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| D | imx7s.dtsi | 735 clock-names = "pix", "axi";
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| /external/u-boot/board/aristainetos/ |
| D | aristainetos2.cfg | 33 #include "axi.cfg"
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| /external/u-boot/arch/arc/dts/ |
| D | hsdk.dts | 46 "apb-clk", "axi-clk",
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| /external/cldr/tools/cldr-unittest/src/org/unicode/cldr/unittest/data/transformtest/ |
| D | el-Latn-t-el-m0-bgn.txt | 321 αξία axía
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| /external/hyphenation-patterns/hu/ |
| D | hyph-hu.pat.txt | 5370 axió2r
|