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1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6ul-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include "imx6ul-pinfunc.h"
14#include "skeleton.dtsi"
15
16/ {
17	aliases {
18		ethernet0 = &fec1;
19		ethernet1 = &fec2;
20		gpio0 = &gpio1;
21		gpio1 = &gpio2;
22		gpio2 = &gpio3;
23		gpio3 = &gpio4;
24		gpio4 = &gpio5;
25		i2c0 = &i2c1;
26		i2c1 = &i2c2;
27		i2c2 = &i2c3;
28		i2c3 = &i2c4;
29		mmc0 = &usdhc1;
30		mmc1 = &usdhc2;
31		serial0 = &uart1;
32		serial1 = &uart2;
33		serial2 = &uart3;
34		serial3 = &uart4;
35		serial4 = &uart5;
36		serial5 = &uart6;
37		serial6 = &uart7;
38		serial7 = &uart8;
39		sai1 = &sai1;
40		sai2 = &sai2;
41		sai3 = &sai3;
42		spi0 = &ecspi1;
43		spi1 = &ecspi2;
44		spi2 = &ecspi3;
45		spi3 = &ecspi4;
46		usbotg0 = &usbotg1;
47		usbotg1 = &usbotg2;
48		usbphy0 = &usbphy1;
49		usbphy1 = &usbphy2;
50	};
51
52	cpus {
53		#address-cells = <1>;
54		#size-cells = <0>;
55
56		cpu0: cpu@0 {
57			compatible = "arm,cortex-a7";
58			device_type = "cpu";
59			reg = <0>;
60			clock-latency = <61036>; /* two CLK32 periods */
61			operating-points = <
62				/* kHz	uV */
63				528000	1175000
64				396000	1025000
65				198000	950000
66			>;
67			fsl,soc-operating-points = <
68				/* KHz	uV */
69				528000	1175000
70				396000	1175000
71				198000	1175000
72			>;
73			clocks = <&clks IMX6UL_CLK_ARM>,
74				 <&clks IMX6UL_CLK_PLL2_BUS>,
75				 <&clks IMX6UL_CLK_PLL2_PFD2>,
76				 <&clks IMX6UL_CA7_SECONDARY_SEL>,
77				 <&clks IMX6UL_CLK_STEP>,
78				 <&clks IMX6UL_CLK_PLL1_SW>,
79				 <&clks IMX6UL_CLK_PLL1_SYS>,
80				 <&clks IMX6UL_PLL1_BYPASS>,
81				 <&clks IMX6UL_CLK_PLL1>,
82				 <&clks IMX6UL_PLL1_BYPASS_SRC>,
83				 <&clks IMX6UL_CLK_OSC>;
84			clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
85				      "secondary_sel", "step", "pll1_sw",
86				      "pll1_sys", "pll1_bypass", "pll1",
87				      "pll1_bypass_src", "osc";
88			arm-supply = <&reg_arm>;
89			soc-supply = <&reg_soc>;
90		};
91	};
92
93	intc: interrupt-controller@00a01000 {
94		compatible = "arm,cortex-a7-gic";
95		#interrupt-cells = <3>;
96		interrupt-controller;
97		reg = <0x00a01000 0x1000>,
98		      <0x00a02000 0x1000>,
99		      <0x00a04000 0x2000>,
100		      <0x00a06000 0x2000>;
101	};
102
103	ckil: clock-cli {
104		compatible = "fixed-clock";
105		#clock-cells = <0>;
106		clock-frequency = <32768>;
107		clock-output-names = "ckil";
108	};
109
110	osc: clock-osc {
111		compatible = "fixed-clock";
112		#clock-cells = <0>;
113		clock-frequency = <24000000>;
114		clock-output-names = "osc";
115	};
116
117	ipp_di0: clock-di0 {
118		compatible = "fixed-clock";
119		#clock-cells = <0>;
120		clock-frequency = <0>;
121		clock-output-names = "ipp_di0";
122	};
123
124	ipp_di1: clock-di1 {
125		compatible = "fixed-clock";
126		#clock-cells = <0>;
127		clock-frequency = <0>;
128		clock-output-names = "ipp_di1";
129	};
130
131	soc {
132		#address-cells = <1>;
133		#size-cells = <1>;
134		compatible = "simple-bus";
135		interrupt-parent = <&gpc>;
136		ranges;
137
138		pmu {
139			compatible = "arm,cortex-a7-pmu";
140			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
141			status = "disabled";
142		};
143
144		ocram: sram@00900000 {
145			compatible = "mmio-sram";
146			reg = <0x00900000 0x20000>;
147		};
148
149		dma_apbh: dma-apbh@01804000 {
150			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
151			reg = <0x01804000 0x2000>;
152			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
153				     <0 13 IRQ_TYPE_LEVEL_HIGH>,
154				     <0 13 IRQ_TYPE_LEVEL_HIGH>,
155				     <0 13 IRQ_TYPE_LEVEL_HIGH>;
156			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
157			#dma-cells = <1>;
158			dma-channels = <4>;
159			clocks = <&clks IMX6UL_CLK_APBHDMA>;
160		};
161
162		gpmi: gpmi-nand@01806000         {
163			compatible = "fsl,imx6q-gpmi-nand";
164			#address-cells = <1>;
165			#size-cells = <1>;
166			reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
167			reg-names = "gpmi-nand", "bch";
168			interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
169			interrupt-names = "bch";
170			clocks = <&clks IMX6UL_CLK_GPMI_IO>,
171				 <&clks IMX6UL_CLK_GPMI_APB>,
172				 <&clks IMX6UL_CLK_GPMI_BCH>,
173				 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
174				 <&clks IMX6UL_CLK_PER_BCH>;
175			clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
176				      "gpmi_bch_apb", "per1_bch";
177			dmas = <&dma_apbh 0>;
178			dma-names = "rx-tx";
179			status = "disabled";
180		};
181
182		aips1: aips-bus@02000000 {
183			compatible = "fsl,aips-bus", "simple-bus";
184			#address-cells = <1>;
185			#size-cells = <1>;
186			reg = <0x02000000 0x100000>;
187			ranges;
188
189			spba-bus@02000000 {
190				compatible = "fsl,spba-bus", "simple-bus";
191				#address-cells = <1>;
192				#size-cells = <1>;
193				reg = <0x02000000 0x40000>;
194				ranges;
195				u-boot,dm-spl;
196
197				ecspi1: ecspi@02008000 {
198					#address-cells = <1>;
199					#size-cells = <0>;
200					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
201					reg = <0x02008000 0x4000>;
202					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
203					clocks = <&clks IMX6UL_CLK_ECSPI1>,
204						 <&clks IMX6UL_CLK_ECSPI1>;
205					clock-names = "ipg", "per";
206					status = "disabled";
207				};
208
209				ecspi2: ecspi@0200c000 {
210					#address-cells = <1>;
211					#size-cells = <0>;
212					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
213					reg = <0x0200c000 0x4000>;
214					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
215					clocks = <&clks IMX6UL_CLK_ECSPI2>,
216						 <&clks IMX6UL_CLK_ECSPI2>;
217					clock-names = "ipg", "per";
218					status = "disabled";
219				};
220
221				ecspi3: ecspi@02010000 {
222					#address-cells = <1>;
223					#size-cells = <0>;
224					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
225					reg = <0x02010000 0x4000>;
226					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
227					clocks = <&clks IMX6UL_CLK_ECSPI3>,
228						 <&clks IMX6UL_CLK_ECSPI3>;
229					clock-names = "ipg", "per";
230					status = "disabled";
231				};
232
233				ecspi4: ecspi@02014000 {
234					#address-cells = <1>;
235					#size-cells = <0>;
236					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
237					reg = <0x02014000 0x4000>;
238					interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
239					clocks = <&clks IMX6UL_CLK_ECSPI4>,
240						 <&clks IMX6UL_CLK_ECSPI4>;
241					clock-names = "ipg", "per";
242					status = "disabled";
243				};
244
245				uart7: serial@02018000 {
246					compatible = "fsl,imx6ul-uart",
247						     "fsl,imx6q-uart";
248					reg = <0x02018000 0x4000>;
249					interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
250					clocks = <&clks IMX6UL_CLK_UART7_IPG>,
251						 <&clks IMX6UL_CLK_UART7_SERIAL>;
252					clock-names = "ipg", "per";
253					status = "disabled";
254				};
255
256				uart1: serial@02020000 {
257					compatible = "fsl,imx6ul-uart",
258						     "fsl,imx6q-uart";
259					reg = <0x02020000 0x4000>;
260					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
261					clocks = <&clks IMX6UL_CLK_UART1_IPG>,
262						 <&clks IMX6UL_CLK_UART1_SERIAL>;
263					clock-names = "ipg", "per";
264					status = "disabled";
265				};
266
267				uart8: serial@02024000 {
268					compatible = "fsl,imx6ul-uart",
269						     "fsl,imx6q-uart";
270					reg = <0x02024000 0x4000>;
271					interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
272					clocks = <&clks IMX6UL_CLK_UART8_IPG>,
273						 <&clks IMX6UL_CLK_UART8_SERIAL>;
274					clock-names = "ipg", "per";
275					status = "disabled";
276				};
277
278				sai1: sai@02028000 {
279					#sound-dai-cells = <0>;
280					compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
281					reg = <0x02028000 0x4000>;
282					interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
283					clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
284						 <&clks IMX6UL_CLK_SAI1>,
285						 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
286					clock-names = "bus", "mclk1", "mclk2", "mclk3";
287					dmas = <&sdma 35 24 0>,
288					       <&sdma 36 24 0>;
289					dma-names = "rx", "tx";
290					status = "disabled";
291				};
292
293				sai2: sai@0202c000 {
294					#sound-dai-cells = <0>;
295					compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
296					reg = <0x0202c000 0x4000>;
297					interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
298					clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
299						 <&clks IMX6UL_CLK_SAI2>,
300						 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
301					clock-names = "bus", "mclk1", "mclk2", "mclk3";
302					dmas = <&sdma 37 24 0>,
303					       <&sdma 38 24 0>;
304					dma-names = "rx", "tx";
305					status = "disabled";
306				};
307
308				sai3: sai@02030000 {
309					#sound-dai-cells = <0>;
310					compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
311					reg = <0x02030000 0x4000>;
312					interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
313					clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
314						 <&clks IMX6UL_CLK_SAI3>,
315						 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
316					clock-names = "bus", "mclk1", "mclk2", "mclk3";
317					dmas = <&sdma 39 24 0>,
318					       <&sdma 40 24 0>;
319					dma-names = "rx", "tx";
320					status = "disabled";
321				};
322			};
323
324			tsc: tsc@02040000 {
325				compatible = "fsl,imx6ul-tsc";
326				reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
327				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
328					     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
329				clocks = <&clks IMX6UL_CLK_IPG>,
330					 <&clks IMX6UL_CLK_ADC2>;
331				clock-names = "tsc", "adc";
332				status = "disabled";
333			};
334
335			pwm1: pwm@02080000 {
336				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
337				reg = <0x02080000 0x4000>;
338				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
339				clocks = <&clks IMX6UL_CLK_PWM1>,
340					 <&clks IMX6UL_CLK_PWM1>;
341				clock-names = "ipg", "per";
342				#pwm-cells = <2>;
343				status = "disabled";
344			};
345
346			pwm2: pwm@02084000 {
347				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
348				reg = <0x02084000 0x4000>;
349				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
350				clocks = <&clks IMX6UL_CLK_PWM2>,
351					 <&clks IMX6UL_CLK_PWM2>;
352				clock-names = "ipg", "per";
353				#pwm-cells = <2>;
354				status = "disabled";
355			};
356
357			pwm3: pwm@02088000 {
358				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
359				reg = <0x02088000 0x4000>;
360				interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
361				clocks = <&clks IMX6UL_CLK_PWM3>,
362					 <&clks IMX6UL_CLK_PWM3>;
363				clock-names = "ipg", "per";
364				#pwm-cells = <2>;
365				status = "disabled";
366			};
367
368			pwm4: pwm@0208c000 {
369				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
370				reg = <0x0208c000 0x4000>;
371				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
372				clocks = <&clks IMX6UL_CLK_PWM4>,
373					 <&clks IMX6UL_CLK_PWM4>;
374				clock-names = "ipg", "per";
375				#pwm-cells = <2>;
376				status = "disabled";
377			};
378
379			can1: flexcan@02090000 {
380				compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
381				reg = <0x02090000 0x4000>;
382				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
383				clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
384					 <&clks IMX6UL_CLK_CAN1_SERIAL>;
385				clock-names = "ipg", "per";
386				status = "disabled";
387			};
388
389			can2: flexcan@02094000 {
390				compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
391				reg = <0x02094000 0x4000>;
392				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
393				clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
394					 <&clks IMX6UL_CLK_CAN2_SERIAL>;
395				clock-names = "ipg", "per";
396				status = "disabled";
397			};
398
399			gpt1: gpt@02098000 {
400				compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
401				reg = <0x02098000 0x4000>;
402				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
403				clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
404					 <&clks IMX6UL_CLK_GPT1_SERIAL>;
405				clock-names = "ipg", "per";
406			};
407
408			gpio1: gpio@0209c000 {
409				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
410				reg = <0x0209c000 0x4000>;
411				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
412					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
413				gpio-controller;
414				#gpio-cells = <2>;
415				interrupt-controller;
416				#interrupt-cells = <2>;
417				gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
418					      <&iomuxc 16 33 16>;
419			};
420
421			gpio2: gpio@020a0000 {
422				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
423				reg = <0x020a0000 0x4000>;
424				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
425					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
426				gpio-controller;
427				#gpio-cells = <2>;
428				interrupt-controller;
429				#interrupt-cells = <2>;
430				gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
431			};
432
433			gpio3: gpio@020a4000 {
434				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
435				reg = <0x020a4000 0x4000>;
436				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
437					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
438				gpio-controller;
439				#gpio-cells = <2>;
440				interrupt-controller;
441				#interrupt-cells = <2>;
442				gpio-ranges = <&iomuxc 0 65 29>;
443			};
444
445			gpio4: gpio@020a8000 {
446				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
447				reg = <0x020a8000 0x4000>;
448				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
449					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
450				gpio-controller;
451				#gpio-cells = <2>;
452				interrupt-controller;
453				#interrupt-cells = <2>;
454				gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
455			};
456
457			gpio5: gpio@020ac000 {
458				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
459				reg = <0x020ac000 0x4000>;
460				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
461					     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
462				gpio-controller;
463				#gpio-cells = <2>;
464				interrupt-controller;
465				#interrupt-cells = <2>;
466				gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
467			};
468
469			fec2: ethernet@020b4000 {
470				compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
471				reg = <0x020b4000 0x4000>;
472				interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
473					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
474				clocks = <&clks IMX6UL_CLK_ENET>,
475					 <&clks IMX6UL_CLK_ENET_AHB>,
476					 <&clks IMX6UL_CLK_ENET_PTP>,
477					 <&clks IMX6UL_CLK_ENET2_REF_125M>,
478					 <&clks IMX6UL_CLK_ENET2_REF_125M>;
479				clock-names = "ipg", "ahb", "ptp",
480					      "enet_clk_ref", "enet_out";
481				fsl,num-tx-queues=<1>;
482				fsl,num-rx-queues=<1>;
483				status = "disabled";
484			};
485
486			kpp: kpp@020b8000 {
487				compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
488				reg = <0x020b8000 0x4000>;
489				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
490				clocks = <&clks IMX6UL_CLK_KPP>;
491				status = "disabled";
492			};
493
494			wdog1: wdog@020bc000 {
495				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
496				reg = <0x020bc000 0x4000>;
497				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
498				clocks = <&clks IMX6UL_CLK_WDOG1>;
499			};
500
501			wdog2: wdog@020c0000 {
502				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
503				reg = <0x020c0000 0x4000>;
504				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
505				clocks = <&clks IMX6UL_CLK_WDOG2>;
506				status = "disabled";
507			};
508
509			clks: ccm@020c4000 {
510				compatible = "fsl,imx6ul-ccm";
511				reg = <0x020c4000 0x4000>;
512				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
513					     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
514				#clock-cells = <1>;
515				clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
516				clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
517			};
518
519			anatop: anatop@020c8000 {
520				compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
521					     "syscon", "simple-bus";
522				reg = <0x020c8000 0x1000>;
523				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
524					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
525					     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
526
527				reg_3p0: regulator-3p0 {
528					compatible = "fsl,anatop-regulator";
529					regulator-name = "vdd3p0";
530					regulator-min-microvolt = <2625000>;
531					regulator-max-microvolt = <3400000>;
532					anatop-reg-offset = <0x120>;
533					anatop-vol-bit-shift = <8>;
534					anatop-vol-bit-width = <5>;
535					anatop-min-bit-val = <0>;
536					anatop-min-voltage = <2625000>;
537					anatop-max-voltage = <3400000>;
538					anatop-enable-bit = <0>;
539				};
540
541				reg_arm: regulator-vddcore {
542					compatible = "fsl,anatop-regulator";
543					regulator-name = "cpu";
544					regulator-min-microvolt = <725000>;
545					regulator-max-microvolt = <1450000>;
546					regulator-always-on;
547					anatop-reg-offset = <0x140>;
548					anatop-vol-bit-shift = <0>;
549					anatop-vol-bit-width = <5>;
550					anatop-delay-reg-offset = <0x170>;
551					anatop-delay-bit-shift = <24>;
552					anatop-delay-bit-width = <2>;
553					anatop-min-bit-val = <1>;
554					anatop-min-voltage = <725000>;
555					anatop-max-voltage = <1450000>;
556				};
557
558				reg_soc: regulator-vddsoc {
559					compatible = "fsl,anatop-regulator";
560					regulator-name = "vddsoc";
561					regulator-min-microvolt = <725000>;
562					regulator-max-microvolt = <1450000>;
563					regulator-always-on;
564					anatop-reg-offset = <0x140>;
565					anatop-vol-bit-shift = <18>;
566					anatop-vol-bit-width = <5>;
567					anatop-delay-reg-offset = <0x170>;
568					anatop-delay-bit-shift = <28>;
569					anatop-delay-bit-width = <2>;
570					anatop-min-bit-val = <1>;
571					anatop-min-voltage = <725000>;
572					anatop-max-voltage = <1450000>;
573				};
574			};
575
576			usbphy1: usbphy@020c9000 {
577				compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
578				reg = <0x020c9000 0x1000>;
579				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
580				clocks = <&clks IMX6UL_CLK_USBPHY1>;
581				phy-3p0-supply = <&reg_3p0>;
582				fsl,anatop = <&anatop>;
583			};
584
585			usbphy2: usbphy@020ca000 {
586				compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
587				reg = <0x020ca000 0x1000>;
588				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
589				clocks = <&clks IMX6UL_CLK_USBPHY2>;
590				phy-3p0-supply = <&reg_3p0>;
591				fsl,anatop = <&anatop>;
592			};
593
594			snvs: snvs@020cc000 {
595				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
596				reg = <0x020cc000 0x4000>;
597
598				snvs_rtc: snvs-rtc-lp {
599					compatible = "fsl,sec-v4.0-mon-rtc-lp";
600					regmap = <&snvs>;
601					offset = <0x34>;
602					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
603						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
604				};
605
606				snvs_poweroff: snvs-poweroff {
607					compatible = "syscon-poweroff";
608					regmap = <&snvs>;
609					offset = <0x38>;
610					mask = <0x60>;
611					status = "disabled";
612				};
613
614				snvs_pwrkey: snvs-powerkey {
615					compatible = "fsl,sec-v4.0-pwrkey";
616					regmap = <&snvs>;
617					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
618					linux,keycode = <KEY_POWER>;
619					wakeup-source;
620				};
621			};
622
623			epit1: epit@020d0000 {
624				reg = <0x020d0000 0x4000>;
625				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
626			};
627
628			epit2: epit@020d4000 {
629				reg = <0x020d4000 0x4000>;
630				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
631			};
632
633			src: src@020d8000 {
634				compatible = "fsl,imx6ul-src", "fsl,imx51-src";
635				reg = <0x020d8000 0x4000>;
636				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
637					     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
638				#reset-cells = <1>;
639			};
640
641			gpc: gpc@020dc000 {
642				compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
643				reg = <0x020dc000 0x4000>;
644				interrupt-controller;
645				#interrupt-cells = <3>;
646				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
647				interrupt-parent = <&intc>;
648			};
649
650			iomuxc: iomuxc@020e0000 {
651				compatible = "fsl,imx6ul-iomuxc";
652				reg = <0x020e0000 0x4000>;
653			};
654
655			gpr: iomuxc-gpr@020e4000 {
656				compatible = "fsl,imx6ul-iomuxc-gpr",
657					     "fsl,imx6q-iomuxc-gpr", "syscon";
658				reg = <0x020e4000 0x4000>;
659			};
660
661			gpt2: gpt@020e8000 {
662				compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
663				reg = <0x020e8000 0x4000>;
664				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
665				clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
666					 <&clks IMX6UL_CLK_GPT2_SERIAL>;
667				clock-names = "ipg", "per";
668			};
669
670			sdma: sdma@020ec000 {
671				compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
672					     "fsl,imx35-sdma";
673				reg = <0x020ec000 0x4000>;
674				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
675				clocks = <&clks IMX6UL_CLK_SDMA>,
676					 <&clks IMX6UL_CLK_SDMA>;
677				clock-names = "ipg", "ahb";
678				#dma-cells = <3>;
679				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
680			};
681
682			pwm5: pwm@020f0000 {
683				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
684				reg = <0x020f0000 0x4000>;
685				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
686				clocks = <&clks IMX6UL_CLK_PWM5>,
687					 <&clks IMX6UL_CLK_PWM5>;
688				clock-names = "ipg", "per";
689				#pwm-cells = <2>;
690				status = "disabled";
691			};
692
693			pwm6: pwm@020f4000 {
694				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
695				reg = <0x020f4000 0x4000>;
696				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
697				clocks = <&clks IMX6UL_CLK_PWM6>,
698					 <&clks IMX6UL_CLK_PWM6>;
699				clock-names = "ipg", "per";
700				#pwm-cells = <2>;
701				status = "disabled";
702			};
703
704			pwm7: pwm@020f8000 {
705				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
706				reg = <0x020f8000 0x4000>;
707				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
708				clocks = <&clks IMX6UL_CLK_PWM7>,
709					 <&clks IMX6UL_CLK_PWM7>;
710				clock-names = "ipg", "per";
711				#pwm-cells = <2>;
712				status = "disabled";
713			};
714
715			pwm8: pwm@020fc000 {
716				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
717				reg = <0x020fc000 0x4000>;
718				interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
719				clocks = <&clks IMX6UL_CLK_PWM8>,
720					 <&clks IMX6UL_CLK_PWM8>;
721				clock-names = "ipg", "per";
722				#pwm-cells = <2>;
723				status = "disabled";
724			};
725		};
726
727		aips2: aips-bus@02100000 {
728			compatible = "fsl,aips-bus", "simple-bus";
729			#address-cells = <1>;
730			#size-cells = <1>;
731			reg = <0x02100000 0x100000>;
732			ranges;
733
734			usbotg1: usb@02184000 {
735				compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
736				reg = <0x02184000 0x200>;
737				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
738				clocks = <&clks IMX6UL_CLK_USBOH3>;
739				fsl,usbphy = <&usbphy1>;
740				fsl,usbmisc = <&usbmisc 0>;
741				fsl,anatop = <&anatop>;
742				ahb-burst-config = <0x0>;
743				tx-burst-size-dword = <0x10>;
744				rx-burst-size-dword = <0x10>;
745				status = "disabled";
746			};
747
748			usbotg2: usb@02184200 {
749				compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
750				reg = <0x02184200 0x200>;
751				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
752				clocks = <&clks IMX6UL_CLK_USBOH3>;
753				fsl,usbphy = <&usbphy2>;
754				fsl,usbmisc = <&usbmisc 1>;
755				ahb-burst-config = <0x0>;
756				tx-burst-size-dword = <0x10>;
757				rx-burst-size-dword = <0x10>;
758				status = "disabled";
759			};
760
761			usbmisc: usbmisc@02184800 {
762				#index-cells = <1>;
763				compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
764				reg = <0x02184800 0x200>;
765			};
766
767			fec1: ethernet@02188000 {
768				compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
769				reg = <0x02188000 0x4000>;
770				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
771					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
772				clocks = <&clks IMX6UL_CLK_ENET>,
773					 <&clks IMX6UL_CLK_ENET_AHB>,
774					 <&clks IMX6UL_CLK_ENET_PTP>,
775					 <&clks IMX6UL_CLK_ENET_REF>,
776					 <&clks IMX6UL_CLK_ENET_REF>;
777				clock-names = "ipg", "ahb", "ptp",
778					      "enet_clk_ref", "enet_out";
779				fsl,num-tx-queues=<1>;
780				fsl,num-rx-queues=<1>;
781				status = "disabled";
782			};
783
784			usdhc1: usdhc@02190000 {
785				compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
786				reg = <0x02190000 0x4000>;
787				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
788				clocks = <&clks IMX6UL_CLK_USDHC1>,
789					 <&clks IMX6UL_CLK_USDHC1>,
790					 <&clks IMX6UL_CLK_USDHC1>;
791				clock-names = "ipg", "ahb", "per";
792				bus-width = <4>;
793				status = "disabled";
794			};
795
796			usdhc2: usdhc@02194000 {
797				compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
798				reg = <0x02194000 0x4000>;
799				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
800				clocks = <&clks IMX6UL_CLK_USDHC2>,
801					 <&clks IMX6UL_CLK_USDHC2>,
802					 <&clks IMX6UL_CLK_USDHC2>;
803				clock-names = "ipg", "ahb", "per";
804				bus-width = <4>;
805				status = "disabled";
806			};
807
808			adc1: adc@02198000 {
809				compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
810				reg = <0x02198000 0x4000>;
811				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
812				clocks = <&clks IMX6UL_CLK_ADC1>;
813				num-channels = <2>;
814				clock-names = "adc";
815				fsl,adck-max-frequency = <30000000>, <40000000>,
816							 <20000000>;
817				status = "disabled";
818			};
819
820			i2c1: i2c@021a0000 {
821				#address-cells = <1>;
822				#size-cells = <0>;
823				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
824				reg = <0x021a0000 0x4000>;
825				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
826				clocks = <&clks IMX6UL_CLK_I2C1>;
827				status = "disabled";
828			};
829
830			i2c2: i2c@021a4000 {
831				#address-cells = <1>;
832				#size-cells = <0>;
833				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
834				reg = <0x021a4000 0x4000>;
835				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
836				clocks = <&clks IMX6UL_CLK_I2C2>;
837				status = "disabled";
838			};
839
840			i2c3: i2c@021a8000 {
841				#address-cells = <1>;
842				#size-cells = <0>;
843				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
844				reg = <0x021a8000 0x4000>;
845				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
846				clocks = <&clks IMX6UL_CLK_I2C3>;
847				status = "disabled";
848			};
849
850			mmdc: mmdc@021b0000 {
851				compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
852				reg = <0x021b0000 0x4000>;
853			};
854
855			lcdif: lcdif@021c8000 {
856				compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
857				reg = <0x021c8000 0x4000>;
858				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
859				clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
860					 <&clks IMX6UL_CLK_LCDIF_APB>,
861					 <&clks IMX6UL_CLK_DUMMY>;
862				clock-names = "pix", "axi", "disp_axi";
863				status = "disabled";
864			};
865
866			qspi: qspi@021e0000 {
867				#address-cells = <1>;
868				#size-cells = <0>;
869				compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
870				reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
871				reg-names = "QuadSPI", "QuadSPI-memory";
872				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
873				clocks = <&clks IMX6UL_CLK_QSPI>,
874					 <&clks IMX6UL_CLK_QSPI>;
875				clock-names = "qspi_en", "qspi";
876				status = "disabled";
877			};
878
879			wdog3: wdog@021e4000 {
880				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
881				reg = <0x021e4000 0x4000>;
882				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
883				clocks = <&clks IMX6UL_CLK_WDOG3>;
884				status = "disabled";
885			};
886
887			uart2: serial@021e8000 {
888				compatible = "fsl,imx6ul-uart",
889					     "fsl,imx6q-uart";
890				reg = <0x021e8000 0x4000>;
891				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
892				clocks = <&clks IMX6UL_CLK_UART2_IPG>,
893					 <&clks IMX6UL_CLK_UART2_SERIAL>;
894				clock-names = "ipg", "per";
895				status = "disabled";
896			};
897
898			uart3: serial@021ec000 {
899				compatible = "fsl,imx6ul-uart",
900					     "fsl,imx6q-uart";
901				reg = <0x021ec000 0x4000>;
902				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
903				clocks = <&clks IMX6UL_CLK_UART3_IPG>,
904					 <&clks IMX6UL_CLK_UART3_SERIAL>;
905				clock-names = "ipg", "per";
906				status = "disabled";
907			};
908
909			uart4: serial@021f0000 {
910				compatible = "fsl,imx6ul-uart",
911					     "fsl,imx6q-uart";
912				reg = <0x021f0000 0x4000>;
913				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
914				clocks = <&clks IMX6UL_CLK_UART4_IPG>,
915					 <&clks IMX6UL_CLK_UART4_SERIAL>;
916				clock-names = "ipg", "per";
917				status = "disabled";
918			};
919
920			uart5: serial@021f4000 {
921				compatible = "fsl,imx6ul-uart",
922					     "fsl,imx6q-uart";
923				reg = <0x021f4000 0x4000>;
924				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
925				clocks = <&clks IMX6UL_CLK_UART5_IPG>,
926					 <&clks IMX6UL_CLK_UART5_SERIAL>;
927				clock-names = "ipg", "per";
928				status = "disabled";
929			};
930
931			i2c4: i2c@021f8000 {
932				#address-cells = <1>;
933				#size-cells = <0>;
934				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
935				reg = <0x021f8000 0x4000>;
936				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
937				clocks = <&clks IMX6UL_CLK_I2C4>;
938				status = "disabled";
939			};
940
941			uart6: serial@021fc000 {
942				compatible = "fsl,imx6ul-uart",
943					     "fsl,imx6q-uart";
944				reg = <0x021fc000 0x4000>;
945				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
946				clocks = <&clks IMX6UL_CLK_UART6_IPG>,
947					 <&clks IMX6UL_CLK_UART6_SERIAL>;
948				clock-names = "ipg", "per";
949				status = "disabled";
950			};
951		};
952	};
953};
954