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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td36 def : AT<"S1E2R", 0b100, 0b0111, 0b1000, 0b000>;
39 def : AT<"S1E2W", 0b100, 0b0111, 0b1000, 0b001>;
43 def : AT<"S12E1R", 0b100, 0b0111, 0b1000, 0b100>;
44 def : AT<"S12E1W", 0b100, 0b0111, 0b1000, 0b101>;
45 def : AT<"S12E0R", 0b100, 0b0111, 0b1000, 0b110>;
46 def : AT<"S12E0W", 0b100, 0b0111, 0b1000, 0b111>;
336 def : TLBI<"IPAS2E1IS", 0b100, 0b1000, 0b0000, 0b001>;
337 def : TLBI<"IPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b101>;
339 def : TLBI<"ALLE2IS", 0b100, 0b1000, 0b0011, 0b000, 0>;
342 def : TLBI<"VAE2IS", 0b100, 0b1000, 0b0011, 0b001>;
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DAArch64SVEInstrInfo.td24 defm SQADD_ZZZ : sve_int_bin_cons_arit_0<0b100, "sqadd">;
46 defm SQADD_ZI : sve_int_arith_imm0<0b100, "sqadd">;
81 defm SDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b100, "sdiv">;
96 defm SXTW_ZPmZ : sve_int_un_pred_arit_0_d<0b100, "sxtw">;
106 defm FABS_ZPmZ : sve_int_un_pred_arit_1_fp<0b100, "fabs">;
113 defm SABD_ZPmZ : sve_int_bin_pred_arit_1<0b100, "sabd">;
123 defm FMAXNM_ZPmI : sve_fp_2op_i_p_zds<0b100, "fmaxnm", sve_fpimm_zero_one>;
175 defm FMAXNMV_VPZ : sve_fp_fast_red<0b100, "fmaxnmv">;
241 defm BRKB_PPzP : sve_int_break_z<0b100, "brkb">;
562 …defm SST1W_D : sve_mem_sst_sv_32_unscaled<0b100, "st1w", Z_d, ZPR64, ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td36 def : AT<"S1E2R", 0b01, 0b100, 0b0111, 0b1000, 0b000>;
39 def : AT<"S1E2W", 0b01, 0b100, 0b0111, 0b1000, 0b001>;
43 def : AT<"S12E1R", 0b01, 0b100, 0b0111, 0b1000, 0b100>;
44 def : AT<"S12E1W", 0b01, 0b100, 0b0111, 0b1000, 0b101>;
45 def : AT<"S12E0R", 0b01, 0b100, 0b0111, 0b1000, 0b110>;
46 def : AT<"S12E0W", 0b01, 0b100, 0b0111, 0b1000, 0b111>;
231 def : TLBI<"IPAS2E1IS", 0b01, 0b100, 0b1000, 0b0000, 0b001>;
232 def : TLBI<"IPAS2LE1IS", 0b01, 0b100, 0b1000, 0b0000, 0b101>;
234 def : TLBI<"ALLE2IS", 0b01, 0b100, 0b1000, 0b0011, 0b000, 0>;
237 def : TLBI<"VAE2IS", 0b01, 0b100, 0b1000, 0b0011, 0b001>;
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/external/libcxx/test/std/language.support/support.types/byteops/
Drshift.pass.cpp27 constexpr std::byte b100{static_cast<std::byte>(100)}; in main() local
30 static_assert(noexcept(b100 << 2), "" ); in main()
32 static_assert(std::to_integer<int>(b100 >> 1) == 50, ""); in main()
33 static_assert(std::to_integer<int>(b100 >> 2) == 25, ""); in main()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoM.td24 def DIV : ALU_rr<0b0000001, 0b100, "div">;
32 def DIVW : ALUW_rr<0b0000001, 0b100, "divw">;
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td177 def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>;
189 def A2_svsubh : T_ALU32_3op<"vsubh", 0b110, 0b100, 1, 0>;
240 def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
843 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
888 def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>;
905 def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>;
910 def A2_vavguwr : T_VectALU_64 < "vavguw", 0b011, 0b100, 0, 1, 0, 0>;
914 def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>;
915 def A2_vnavgw : T_VectALU_64 < "vnavgw", 0b100, 0b011, 0, 0, 0, 1>;
920 def A2_vnavghr : T_VectALU_64 < "vnavgh", 0b100, 0b001, 1, 1, 0, 1>;
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DHexagonInstrInfoV5.td24 def M5_vrmpybuu: T_XTYPE_Vect<"vrmpybu", 0b100, 0b001, 0>;
25 def M5_vrmacbuu: T_XTYPE_Vect_acc<"vrmpybu", 0b100, 0b001, 0>;
35 def M5_vmpybuu: T_XTYPE_mpy64 <"vmpybu", 0b100, 0b001, 0, 0, 0>;
39 def M5_vmacbuu: T_XTYPE_mpy64_acc <"vmpybu", "+", 0b100, 0b001, 0, 0, 0>;
189 def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>;
190 def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>;
280 def F2_sfcmpgt : T_fcmp32<"sfcmp.gt", setogt, 0b100>;
638 def F2_conv_sf2w_chop : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b001,
657 def F2_conv_sf2d : F2_RDD_RS_CONVERT <"convert_sf2d", 0b100,
661 def F2_conv_df2w : F2_RD_RSS_CONVERT <"convert_df2w", 0b100,
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DHexagonInstrInfoV3.td213 let Inst{7-5} = 0b100;
243 let Inst{7-5} = 0b100;
DHexagonSystemInst.td56 "syncht" , [], 0b100, 0b001, 0b0>;
DHexagonIsetDx.td101 let Inst{6-4} = 0b100;
217 let Inst{2-0} = 0b100;
605 let Inst{2-0} = 0b100;
DHexagonInstrInfoV4.td135 def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
190 def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
626 defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
716 def S4_storeri_ap : T_ST_absset <"memw", "STriw", IntRegs, 0b100, WordAccess>;
793 def S4_storeri_ur : T_StoreAbsReg <"memw", "STriw", IntRegs, 0b100, WordAccess>;
1028 defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
1116 let Inst{27-25} = 0b100;
1628 defm J4_cmpltu : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
1743 defm J4_cmpeqn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
1965 def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>;
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DHexagonInstrInfoVector.td79 def S2_asr_i_vh : vshift_v4i16<sra, "vasrh", 0b100, 0b000>;
80 def S2_lsr_i_vh : vshift_v4i16<srl, "vlsrh", 0b100, 0b001>;
81 def S2_asl_i_vh : vshift_v4i16<shl, "vaslh", 0b100, 0b010>;
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td431 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
432 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
433 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
434 class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
441 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
442 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
443 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
444 class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
520 class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
521 class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
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DMipsMSAInstrFormats.td214 let Inst{21-19} = 0b100;
266 let Inst{21-19} = 0b100;
318 let Inst{21-19} = 0b100;
/external/tcpdump/tests/
Dbgp-aigp-oobr-nossl.out143 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
234 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
325 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
416 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
507 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
598 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
689 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
780 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
871 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
962 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
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Dbgp-aigp-oobr-ssl.out143 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
234 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
325 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
416 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
507 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
598 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
689 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
780 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
871 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
962 0x0050: 0041 b100 0049 8a00 0000 5aac 1111 20
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td429 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
430 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
431 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
432 class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
439 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
440 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
441 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
442 class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
518 class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
519 class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
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DMipsMSAInstrFormats.td215 let Inst{21-19} = 0b100;
267 let Inst{21-19} = 0b100;
319 let Inst{21-19} = 0b100;
/external/u-boot/doc/
DREADME.fsl-esdhc13 0b100 reserved
/external/libmtp/logs/
Dmtp-detect-samsung-yp-s3.txt50 01b0: f600 000e f300 0013 b500 0016 b100 001d ................
67 02c0: b500 0016 b100 001d e600 0027 3b00 0029 ...........';..)
78 0370: b500 0016 b100 001e f900 0029 4100 002b ...........)A..+
115 01b0: f600 000e f300 0013 b500 0016 b100 001d ................
132 02c0: b500 0016 b100 001d e600 0027 3b00 0029 ...........';..)
143 0370: b500 0016 b100 001e f900 0029 4100 002b ...........)A..+
/external/mesa3d/src/intel/compiler/
Dbrw_reg_type.c108 GEN10_ALIGN1_3SRC_REG_TYPE_UB = 0b100,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonDepInstrInfo.td153 let Inst{7-5} = 0b100;
203 let Inst{7-5} = 0b100;
453 let Inst{7-5} = 0b100;
463 let Inst{7-5} = 0b100;
507 let Inst{7-5} = 0b100;
1164 let Inst{7-5} = 0b100;
1214 let Inst{7-5} = 0b100;
1711 let Inst{7-5} = 0b100;
1751 let Inst{7-5} = 0b100;
1815 let Inst{7-5} = 0b100;
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/external/mesa3d/src/compiler/glsl/tests/
Darray_refcount_test.cpp677 operand b100 = deref_array( in TEST_F() local
686 b100), in TEST_F()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/
DARCInstrInfo.td421 def SP_ADD_S : F16_SP_OPS_u7_aligned<0b100,
581 def BHI_S : F16_BCC_s7<0b100, "bhi_s">;
615 def BSET_S_ru5 : F16_SH_SUB_BIT_DST<0b100,"bset_s">;
656 F16_OP_HREG_LIMM<0b100, (outs GPR32:$b_s3), (ins i32imm:$LImm),
660 F16_OP_HREG<0b100, (outs GPR32:$b_s3), (ins GPR32:$h),
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb2.td1781 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1787 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1945 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1951 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1960 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1966 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1975 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1981 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
2355 def t2SMLAL : T2MulLong<0b100, 0b0000,
2604 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
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