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Searched refs:beqc (Results 1 – 25 of 40) sorted by relevance

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/external/llvm/test/MC/Disassembler/Mips/mips32r6/
Dvalid-xfail-mips32r6.txt10 0x20 0xc0 0x00 0x40 # CHECK: beqc $6, $zero, 256
11 0x20 0xa0 0x00 0x40 # CHECK: beqc $5, $zero, 256
12 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256
Dvalid-mips32r6-el.txt20 0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 260
Dvalid-mips32r6.txt59 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 260
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips32r6/
Dvalid-xfail-mips32r6.txt10 0x20 0xc0 0x00 0x40 # CHECK: beqc $6, $zero, 256
11 0x20 0xa0 0x00 0x40 # CHECK: beqc $5, $zero, 256
12 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256
Dvalid-mips32r6-el.txt21 0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 260
Dvalid-mips32r6.txt61 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 260
/external/llvm/test/MC/Disassembler/Mips/mips64r6/
Dvalid-xfail-mips64r6.txt10 0x20 0xc0 0x00 0x40 # CHECK: beqc $6, $zero, 260
11 0x20 0xa0 0x00 0x40 # CHECK: beqc $5, $zero, 260
12 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 260
Dvalid-mips64r6-el.txt20 0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 260
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r6/
Dvalid-xfail-mips64r6.txt10 0x20 0xc0 0x00 0x40 # CHECK: beqc $6, $zero, 260
11 0x20 0xa0 0x00 0x40 # CHECK: beqc $5, $zero, 260
12 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 260
Dvalid-mips64r6-el.txt19 0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 260
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/compactbranches/
Dno-beqzc-bnezc.ll40 ; beqc and bnec have the restriction that $rs < $rt.
44 ; ENCODING-NOT: beqc $5, $4
87 ; beqc and bnec have the restriction that $rs < $rt.
91 ; ENCODING-NOT: beqc $5, $4
Dbeqc-bnec-register-constraint.ll5 ; beqc/bnec have the constraint that $rs < $rt && $rs != 0 && $rt != 0
39 ; CHECK-NOT: beqc $[[R1:[0-9]+]], $[[R1]]
76 ; CHECK-NOT: beqc $[[R1:[0-9]+]], $[[R1]]
Dcompact-branches.ll43 ; CHECK: beqc
Dcompact-branches-64.ll41 ; CHECK: beqc
/external/llvm/test/CodeGen/Mips/compactbranches/
Dno-beqzc-bnezc.ll37 ; beqc and bnec have the restriction that $rs < $rt.
41 ; ENCODING-NOT: beqc $5, $4
Dbeqc-bnec-register-constraint.ll3 ; beqc/bnec have the constraint that $rs < $rt && $rs != 0 && $rt != 0
36 ; CHECK-NOT: beqc $[[R1:[0-9]+]], $[[R1]]
Dcompact-branches.ll41 ; CHECK beqc
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r6/
Drelocations.s11 # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
65 beqc $5, $6, bar
/external/llvm/test/MC/Mips/mips32r6/
Drelocations.s11 # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
61 beqc $5, $6, bar
/external/llvm/test/MC/Mips/mips64r6/
Drelocations.s11 # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
66 beqc $5, $6, bar
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r6/
Drelocations.s11 # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
70 beqc $5, $6, bar
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips32r6/
Dinvalid.s319 …beqc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instru…
320 beqc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
321 beqc $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
322 beqc $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
323 beqc $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
324 beqc $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
Dvalid.s32 beqc $3,$4, 16 # CHECK: beqc $3, $4, 16 # encoding: [0x74,0x83,0x00,0x04]
/external/llvm/test/MC/Mips/micromips32r6/
Dvalid.s23 beqc $3,$4, 16 # CHECK: beqc $3, $4, 16 # encoding: [0x74,0x83,0x00,0x08]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td83 class BEQC64_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR64Opnd>;

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