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1//=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes Mips64r6 instructions.
11//
12//===----------------------------------------------------------------------===//
13
14// Notes about removals/changes from MIPS32r6:
15// Reencoded: dclo, dclz
16
17//===----------------------------------------------------------------------===//
18//
19// Instruction Encodings
20//
21//===----------------------------------------------------------------------===//
22
23class DALIGN_ENC  : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;
24class DAUI_ENC    : DAUI_FM;
25class DAHI_ENC    : REGIMM_FM<OPCODE5_DAHI>;
26class DATI_ENC    : REGIMM_FM<OPCODE5_DATI>;
27class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;
28class DCLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLO>;
29class DCLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLZ>;
30class DDIV_ENC    : SPECIAL_3R_FM<0b00010, 0b011110>;
31class DDIVU_ENC   : SPECIAL_3R_FM<0b00010, 0b011111>;
32class DLSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_DLSA>;
33class DMOD_ENC    : SPECIAL_3R_FM<0b00011, 0b011110>;
34class DMODU_ENC   : SPECIAL_3R_FM<0b00011, 0b011111>;
35class DMUH_ENC    : SPECIAL_3R_FM<0b00011, 0b011100>;
36class DMUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b011101>;
37class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011100>;
38class DMULU_ENC   : SPECIAL_3R_FM<0b00010, 0b011101>;
39class LDPC_ENC    : PCREL18_FM<OPCODE3_LDPC>;
40class LLD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LLD>;
41class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;
42class CRC32D_ENC  : SPECIAL3_2R_SZ_CRC<3,0>;
43class CRC32CD_ENC : SPECIAL3_2R_SZ_CRC<3,1>;
44
45//===----------------------------------------------------------------------===//
46//
47// Instruction Descriptions
48//
49//===----------------------------------------------------------------------===//
50
51class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, InstrItinClass itin> {
52  dag OutOperandList = (outs GPROpnd:$rs);
53  dag InOperandList = (ins GPROpnd:$rt, uimm16_altrelaxed:$imm);
54  string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
55  string Constraints = "$rs = $rt";
56  InstrItinClass Itinerary = itin;
57}
58
59class DALIGN_DESC  : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3, II_DALIGN>;
60class DAHI_DESC    : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd, II_DAHI>;
61class DATI_DESC    : AHI_ATI_DESC_BASE<"dati", GPR64Opnd, II_DATI>;
62class DAUI_DESC    : AUI_DESC_BASE<"daui", GPR64Opnd, II_DAUI>;
63class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd, II_DBITSWAP>;
64class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd, II_DCLO>;
65class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd, II_DCLZ>;
66class DDIV_DESC    : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV, sdiv>;
67class DDIVU_DESC   : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, II_DDIVU, udiv>;
68class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2_plus1, II_DLSA>;
69class DMOD_DESC    : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, II_DMOD, srem>;
70class DMODU_DESC   : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, II_DMODU, urem>;
71class DMUH_DESC    : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH, mulhs>;
72class DMUHU_DESC   : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU, mulhu>;
73class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
74class DMULU_DESC   : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>;
75class LDPC_DESC    : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>;
76class LLD_R6_DESC   : LL_R6_DESC_BASE<"lld", GPR64Opnd, mem_simmptr, II_LLD>;
77class SCD_R6_DESC   : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;
78class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
79class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
80
81class BGEC64_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR64Opnd>;
82class BGEUC64_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR64Opnd>;
83class BEQC64_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR64Opnd>;
84class BNEC64_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR64Opnd>;
85class BLTC64_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR64Opnd>;
86class BLTUC64_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR64Opnd>;
87class BLTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR64Opnd>;
88class BGEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR64Opnd>;
89class BLEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR64Opnd>;
90class BGTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR64Opnd>;
91class BEQZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR64Opnd>;
92class BNEZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR64Opnd>;
93
94class JIALC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
95                                               GPR64Opnd, II_JIALC> {
96  bit isCall = 1;
97  list<Register> Defs = [RA];
98}
99
100class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd,
101                                             II_JIC> {
102  bit isBarrier = 1;
103  bit isTerminator = 1;
104  list<Register> Defs = [AT];
105}
106
107class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>;
108class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
109
110class JR_HB64_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR64Opnd> {
111  bit isBranch = 1;
112  bit isIndirectBranch = 1;
113  bit hasDelaySlot = 1;
114  bit isTerminator=1;
115  bit isBarrier=1;
116  bit isCTI = 1;
117  InstrItinClass Itinerary = II_JR_HB;
118}
119
120class CRC32D_DESC  : CRC_DESC_BASE<"crc32d", GPR32Opnd, II_CRC32D>;
121class CRC32CD_DESC : CRC_DESC_BASE<"crc32cd", GPR32Opnd, II_CRC32CD>;
122
123//===----------------------------------------------------------------------===//
124//
125// Instruction Definitions
126//
127//===----------------------------------------------------------------------===//
128
129let AdditionalPredicates = [NotInMicroMips] in {
130  let DecoderMethod = "DecodeDAHIDATI" in {
131    def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
132    def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
133  }
134  def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
135  def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
136  def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
137  def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
138  def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
139  def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
140  def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
141  def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
142  def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
143  def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
144  def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
145  def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
146  def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
147  def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
148  def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;
149}
150def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
151def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
152let DecoderNamespace = "Mips32r6_64r6_GP64" in {
153  def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
154  def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
155  def JR_HB64_R6 : JR_HB_R6_ENC, JR_HB64_R6_DESC, ISA_MIPS32R6;
156}
157let AdditionalPredicates = [NotInMicroMips],
158    DecoderNamespace = "Mips32r6_64r6_PTR64" in {
159  def LL64_R6 : LL_R6_ENC, LL64_R6_DESC, PTR_64, ISA_MIPS64R6;
160  def SC64_R6 : SC_R6_ENC, SC64_R6_DESC, PTR_64, ISA_MIPS64R6;
161}
162
163let DecoderNamespace = "Mips32r6_64r6_GP64" in {
164// Jump and Branch Instructions
165def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6, GPR_64;
166def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6, GPR_64;
167
168def BEQC64 : BEQC_ENC, BEQC64_DESC, ISA_MIPS64R6, GPR_64;
169def BEQZC64 : BEQZC_ENC, BEQZC64_DESC, ISA_MIPS64R6, GPR_64;
170def BGEC64 : BGEC_ENC, BGEC64_DESC, ISA_MIPS64R6, GPR_64;
171def BGEUC64 : BGEUC_ENC, BGEUC64_DESC, ISA_MIPS64R6, GPR_64;
172def BGTZC64 : BGTZC_ENC, BGTZC64_DESC, ISA_MIPS64R6, GPR_64;
173def BLEZC64 : BLEZC_ENC, BLEZC64_DESC, ISA_MIPS64R6, GPR_64;
174def BLTC64 : BLTC_ENC, BLTC64_DESC, ISA_MIPS64R6, GPR_64;
175def BLTUC64 : BLTUC_ENC, BLTUC64_DESC, ISA_MIPS64R6, GPR_64;
176def BNEC64 : BNEC_ENC, BNEC64_DESC, ISA_MIPS64R6, GPR_64;
177def BNEZC64 : BNEZC_ENC, BNEZC64_DESC, ISA_MIPS64R6, GPR_64;
178}
179let DecoderNamespace = "Mips32r6_64r6_BranchZero" in {
180def BLTZC64 : BLTZC_ENC, BLTZC64_DESC, ISA_MIPS64R6, GPR_64;
181def BGEZC64 : BGEZC_ENC, BGEZC64_DESC, ISA_MIPS64R6, GPR_64;
182}
183let AdditionalPredicates = [NotInMicroMips] in {
184  def CRC32D : R6MMR6Rel, CRC32D_ENC, CRC32D_DESC, ISA_MIPS64R6, ASE_CRC;
185  def CRC32CD : R6MMR6Rel, CRC32CD_ENC, CRC32CD_DESC, ISA_MIPS64R6, ASE_CRC;
186}
187
188//===----------------------------------------------------------------------===//
189//
190// Instruction Aliases
191//
192//===----------------------------------------------------------------------===//
193
194def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
195
196def : MipsInstAlias<"jrc $rs", (JIC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;
197
198def : MipsInstAlias<"jalrc $rs", (JIALC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;
199//===----------------------------------------------------------------------===//
200//
201// Patterns and Pseudo Instructions
202//
203//===----------------------------------------------------------------------===//
204
205// i64 selects
206def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
207              (OR64 (SELNEZ64 i64:$t, i64:$cond),
208                    (SELEQZ64 i64:$f, i64:$cond))>,
209              ISA_MIPS64R6;
210def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
211              (OR64 (SELEQZ64 i64:$t, i64:$cond),
212                    (SELNEZ64 i64:$f, i64:$cond))>,
213              ISA_MIPS64R6;
214def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
215              (OR64 (SELNEZ64 i64:$t, i64:$cond),
216                    (SELEQZ64 i64:$f, i64:$cond))>,
217              ISA_MIPS64R6;
218def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
219              (OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
220                    (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
221              ISA_MIPS64R6;
222def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
223              (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
224                    (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
225              ISA_MIPS64R6;
226def : MipsPat<
227  (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
228  (OR64 (SELEQZ64 i64:$t,
229                  (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
230                                 sub_32)),
231        (SELNEZ64 i64:$f,
232                  (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
233                                 sub_32)))>,
234  ISA_MIPS64R6;
235def : MipsPat<
236  (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
237  (OR64 (SELEQZ64 i64:$t,
238                  (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
239                                 sub_32)),
240        (SELNEZ64 i64:$f,
241                  (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
242                                 sub_32)))>,
243  ISA_MIPS64R6;
244
245def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),
246              (SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
247def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),
248              (SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
249def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),
250              (SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
251def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),
252              (SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
253
254// i64 selects from an i32 comparison
255// One complicating factor here is that bits 32-63 of an i32 are undefined.
256// FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.
257//        This would allow us to remove the sign-extensions here.
258def : MipsPat<(select i32:$cond, i64:$t, i64:$f),
259              (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
260                    (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
261              ISA_MIPS64R6;
262def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),
263              (OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)),
264                    (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>,
265              ISA_MIPS64R6;
266def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),
267              (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
268                    (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
269              ISA_MIPS64R6;
270def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
271              (OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
272                                                      immZExt16:$imm))),
273                    (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
274                                                      immZExt16:$imm))))>,
275              ISA_MIPS64R6;
276def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
277              (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
278                                                      immZExt16:$imm))),
279                    (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
280                                                      immZExt16:$imm))))>,
281              ISA_MIPS64R6;
282
283def : MipsPat<(select i32:$cond, i64:$t, immz),
284              (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
285              ISA_MIPS64R6;
286def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz),
287              (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
288              ISA_MIPS64R6;
289def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, immz),
290              (SELEQZ64 i64:$t, (SLL64_32 i32:$cond))>,
291              ISA_MIPS64R6;
292def : MipsPat<(select i32:$cond, immz, i64:$f),
293              (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
294              ISA_MIPS64R6;
295def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),
296              (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
297              ISA_MIPS64R6;
298def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),
299              (SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,
300              ISA_MIPS64R6;
301
302// Patterns used for matching away redundant sign extensions.
303// MIPS32 arithmetic instructions sign extend their result implicitly.
304def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))),
305              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
306              (MUL_R6 GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
307def : MipsPat<(i64 (sext (i32 (sdiv GPR32:$src, GPR32:$src2)))),
308              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
309              (DIV GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
310def : MipsPat<(i64 (sext (i32 (udiv GPR32:$src, GPR32:$src2)))),
311              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
312              (DIVU GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
313def : MipsPat<(i64 (sext (i32 (srem GPR32:$src, GPR32:$src2)))),
314              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
315              (MOD GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
316def : MipsPat<(i64 (sext (i32 (urem GPR32:$src, GPR32:$src2)))),
317              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
318              (MODU GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
319
320// Pseudo instructions
321
322let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
323                            NoIndirectJumpGuards] in {
324  def TAILCALL64R6REG : TailCallRegR6<JALR64, ZERO_64, GPR64Opnd>, ISA_MIPS64R6;
325  def PseudoIndirectBranch64R6 : PseudoIndirectBranchBaseR6<JALR64, ZERO_64,
326                                                            GPR64Opnd>,
327                                 ISA_MIPS64R6;
328}
329
330let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
331                            UseIndirectJumpsHazard] in {
332  def TAILCALLHB64R6REG : TailCallReg<JR_HB64_R6, GPR64Opnd>,
333                          ISA_MIPS64R6;
334  def PseudoIndrectHazardBranch64R6 : PseudoIndirectBranchBase<JR_HB64_R6,
335                                                                 GPR64Opnd>,
336                                      ISA_MIPS64R6;
337}
338