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Searched refs:bgeuc (Results 1 – 25 of 25) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips32r6/
Dinvalid.s307 …bgeuc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instru…
308 bgeuc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
309 bgeuc $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
310 bgeuc $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
311 bgeuc $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
312 bgeuc $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
Dvalid.s34 bgeuc $3,$4, 16 # CHECK: bgeuc $3, $4, 16 # encoding: [0xc0,0x83,0x00,0x04]
/external/llvm/test/MC/Disassembler/Mips/mips32r6/
Dvalid-mips32r6-el.txt28 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 260
29 0xfa 0xff 0x43 0x18 # CHECK: bgeuc $2, $3, -20
Dvalid-mips32r6.txt44 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 260
45 0x18 0x43 0xff 0xfa # CHECK: bgeuc $2, $3, -20
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips32r6/
Dvalid-mips32r6-el.txt29 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 260
30 0xfa 0xff 0x43 0x18 # CHECK: bgeuc $2, $3, -20
Dvalid-mips32r6.txt46 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 260
47 0x18 0x43 0xff 0xfa # CHECK: bgeuc $2, $3, -20
/external/llvm/test/MC/Disassembler/Mips/mips64r6/
Dvalid-mips64r6-el.txt26 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 260
27 0xfa 0xff 0x43 0x18 # CHECK: bgeuc $2, $3, -20
Dvalid-mips64r6.txt61 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 260
62 0x18 0x43 0xff 0xfa # CHECK: bgeuc $2, $3, -20
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r6/
Dvalid-mips64r6-el.txt26 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 260
27 0xfa 0xff 0x43 0x18 # CHECK: bgeuc $2, $3, -20
Dvalid-mips64r6.txt63 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 260
64 0x18 0x43 0xff 0xfa # CHECK: bgeuc $2, $3, -20
/external/llvm/test/MC/Mips/micromips32r6/
Dvalid.s25 bgeuc $3,$4, 16 # CHECK: bgeuc $3, $4, 16 # encoding: [0xc0,0x83,0x00,0x08]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td82 class BGEUC64_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR64Opnd>;
DMicroMips32r6InstrInfo.td70 class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>,
331 class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_lsl2_mm,
DMips32r6InstrInfo.td435 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
/external/v8/src/mips/
Dassembler-mips.h719 void bgeuc(Register rs, Register rt, int16_t offset);
720 inline void bgeuc(Register rs, Register rt, Label* L) { in bgeuc() function
721 bgeuc(rs, rt, shifted_branch_offset(L)); in bgeuc()
Dmacro-assembler-mips.cc3062 bgeuc(rs, scratch, offset); in BranchShortHelperR6()
3098 bgeuc(scratch, rs, offset); in BranchShortHelperR6()
Dassembler-mips.cc1618 void Assembler::bgeuc(Register rs, Register rt, int16_t offset) { in bgeuc() function in v8::internal::Assembler
/external/llvm/test/MC/Disassembler/Mips/micromips32r6/
Dvalid.txt44 0xc0 0x83 0x00 0x08 # CHECK: bgeuc $3, $4, 16
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/micromips32r6/
Dvalid.txt44 0xc0 0x83 0x00 0x04 # CHECK: bgeuc $3, $4, 20
/external/v8/src/mips64/
Dassembler-mips64.h729 void bgeuc(Register rs, Register rt, int16_t offset);
730 inline void bgeuc(Register rs, Register rt, Label* L) { in bgeuc() function
731 bgeuc(rs, rt, shifted_branch_offset(L)); in bgeuc()
Dmacro-assembler-mips64.cc3560 bgeuc(rs, scratch, offset); in BranchShortHelperR6()
3596 bgeuc(scratch, rs, offset); in BranchShortHelperR6()
Dassembler-mips64.cc1598 void Assembler::bgeuc(Register rs, Register rt, int16_t offset) { in bgeuc() function in v8::internal::Assembler
/external/llvm/lib/Target/Mips/
DMicroMips32r6InstrInfo.td60 class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>,
282 class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_mm,
DMips32r6InstrInfo.td396 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc4852 "beqzc16\005beqzl\003bge\004bgec\004bgel\004bgeu\005bgeuc\005bgeul\004bg"
5313 …{ 1011 /* bgeuc */, Mips::BGEUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_H…
5314 …{ 1011 /* bgeuc */, Mips::BGEUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feat…
5315 …{ 1011 /* bgeuc */, Mips::BGEUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature…
8200 …{ Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1011 /* bgeuc */, MCK_GPR32AsmReg,…
8201 …{ Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1011 /* bgeuc */, MCK_JumpTarget, …
8202 { Feature_InMicroMips|Feature_HasMips32r6, 1011 /* bgeuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8203 { Feature_InMicroMips|Feature_HasMips32r6, 1011 /* bgeuc */, MCK_JumpTarget, 4 /* 2 */ },
8204 …{ Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1011 /* bgeuc */, MCK_GPR64AsmReg, 3 /*…
8205 …{ Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1011 /* bgeuc */, MCK_JumpTarget, 4 /* …