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Searched refs:bit7 (Results 1 – 25 of 27) sorted by relevance

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/external/u-boot/tools/
Dvybridimage.c49 uint8_t bit7 = (byte & (1 << 7)) ? 1 : 0; in vybridimage_sw_ecc() local
53 res |= ((bit7 ^ bit5 ^ bit4 ^ bit2 ^ bit1) << 1); in vybridimage_sw_ecc()
54 res |= ((bit7 ^ bit6 ^ bit5 ^ bit1 ^ bit0) << 2); in vybridimage_sw_ecc()
55 res |= ((bit7 ^ bit4 ^ bit3 ^ bit0) << 3); in vybridimage_sw_ecc()
/external/u-boot/board/buffalo/lsxl/
Dkwbimage-lsxhl.cfg56 # bit7-4: 4, 5 cycle tRCD
78 # bit7-6: 0, Cs1size=nonexistent
104 # bit7: 0, (Test Mode) Normal operation
128 # bit7: 0 required (???)
139 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
148 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
180 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
195 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
Dkwbimage-lschl.cfg56 # bit7-4: 4, 5 cycle tRCD
78 # bit7-6: 0, Cs1size=nonexistent
104 # bit7: 0, (Test Mode) Normal operation
128 # bit7: 0 required (???)
139 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
148 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
180 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
195 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
/external/u-boot/board/d-link/dns325/
Dkwbimage.cfg53 # bit7-4: 5, 6 cycle tRCD
73 # bit7-6: 0, Cs1size=nonexistent
96 # bit7: 0, (Test Mode) Normal operation
118 # bit7: 0 required
128 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
136 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
162 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
175 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
/external/vixl/src/aarch64/
Dinstructions-aarch64.cc170 uint16_t bit7 = (bits >> 7) & 0x1; in Imm8ToFloat16() local
173 uint16_t result = (bit7 << 15) | ((4 - bit6) << 12) | (bit5_to_0 << 6); in Imm8ToFloat16()
183 uint32_t bit7 = (bits >> 7) & 0x1; in Imm8ToFP32() local
186 uint32_t result = (bit7 << 31) | ((32 - bit6) << 25) | (bit5_to_0 << 19); in Imm8ToFP32()
204 uint64_t bit7 = (bits >> 7) & 0x1; in Imm8ToFP64() local
207 uint64_t result = (bit7 << 63) | ((256 - bit6) << 54) | (bit5_to_0 << 48); in Imm8ToFP64()
Dassembler-aarch64.cc4978 uint16_t bit7 = ((bits >> 15) & 0x1) << 7; in FP16ToImm8() local
4983 uint32_t result = static_cast<uint32_t>(bit7 | bit6 | bit5_to_0); in FP16ToImm8()
4998 uint32_t bit7 = ((bits >> 31) & 0x1) << 7; in FP32ToImm8() local
5004 return bit7 | bit6 | bit5_to_0; in FP32ToImm8()
5017 uint64_t bit7 = ((bits >> 63) & 0x1) << 7; in FP64ToImm8() local
5023 return static_cast<uint32_t>(bit7 | bit6 | bit5_to_0); in FP64ToImm8()
/external/u-boot/board/keymile/km_arm/
Dkwbimage-memphis.cfg67 # bit7-4: TRCD
87 # bit7-6: 00, Cs1size =nonexistent
123 # bit7 : 0
133 # bit7-4 : 0010, M_ODT assertion 2 cycles after read
141 # bit7-4 : 0101, M_ODT de-assertion x cycles after write
168 # bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
Dkwbimage.cfg64 # bit7-4: TRCD
84 # bit7-6: 00, Cs1size =nonexistent
120 # bit7 : 0
153 # bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
/external/u-boot/board/LaCie/netspace_v2/
Dkwbimage-is2.cfg43 # bit7-4: TRCD
63 # bit7-6: 00, Cs1size =nonexistent
86 # bit7: 0, TestMode=0 normal
108 # bit7 : 1 , D2P Latency enabled
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
Dkwbimage.cfg43 # bit7-4: TRCD
63 # bit7-6: 00, Cs1size =nonexistent
86 # bit7: 0, TestMode=0 normal
108 # bit7 : 1 , D2P Latency enabled
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
Dkwbimage-ns2l.cfg43 # bit7-4: TRCD
63 # bit7-6: 00, Cs1size =nonexistent
86 # bit7: 0, TestMode=0 normal
108 # bit7 : 1 , D2P Latency enabled
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
/external/u-boot/board/iomega/iconnect/
Dkwbimage.cfg43 # bit7-4: TRCD
63 # bit7-6: 11, Cs1size (1Gb)
86 # bit7: 0x0, TestMode=0 normal
108 # bit7: 0x0,
135 # bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
/external/u-boot/board/LaCie/net2big_v2/
Dkwbimage.cfg43 # bit7-4: TRCD
63 # bit7-6: 00, Cs1size =nonexistent
86 # bit7: 0, TestMode=0 normal
108 # bit7 : 1 , D2P Latency enabled
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
/external/u-boot/board/cloudengines/pogo_e02/
Dkwbimage.cfg47 # bit7-4: TRCD
67 # bit7-6: 11, Cs1size=1Gb
90 # bit7: 0, TestMode=0 normal
112 # bit7 : 0
139 # bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
/external/u-boot/board/raidsonic/ib62x0/
Dkwbimage.cfg44 # bit7-4: TRCD
64 # bit7-6: 11, Cs1size (1Gb)
87 # bit7: 0x0, TestMode=0 normal
109 # bit7: 0x0,
136 # bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
/external/u-boot/board/Marvell/openrd/
Dkwbimage.cfg43 # bit7-4: TRCD
63 # bit7-6: 11, Cs1size=1Gb
86 # bit7: 0, TestMode=0 normal
108 # bit7 : 0
135 # bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
/external/u-boot/board/Seagate/nas220/
Dkwbimage.cfg47 # bit7-4: TRCD
68 # bit7-6: 00, Cs1size =nonexistent
91 # bit7: 0, TestMode=0 normal
114 # bit7 : 0
/external/u-boot/board/Marvell/guruplug/
Dkwbimage.cfg43 # bit7-4: TRCD
63 # bit7-6: 10, Cs1size=1Gb
86 # bit7: 0, TestMode=0 normal
108 # bit7 : 0
/external/u-boot/board/Seagate/goflexhome/
Dkwbimage.cfg49 # bit7-4: TRCD
69 # bit7-6: 00, Cs1size =nonexistent
92 # bit7: 0, TestMode=0 normal
114 # bit7 : 0
/external/u-boot/board/Marvell/sheevaplug/
Dkwbimage.cfg43 # bit7-4: TRCD
63 # bit7-6: 11, Cs1size=1Gb
86 # bit7: 0, TestMode=0 normal
108 # bit7 : 0
/external/u-boot/board/Synology/ds109/
Dkwbimage.cfg47 # bit7-4: TRCD
67 # bit7-6: 10, Cs1size=1Gb
90 # bit7: 0, TestMode=0 normal
112 # bit7 : 0
/external/u-boot/board/Seagate/dockstar/
Dkwbimage.cfg46 # bit7-4: TRCD
66 # bit7-6: 00, Cs1size =nonexistent
89 # bit7: 0, TestMode=0 normal
111 # bit7 : 0
/external/u-boot/board/Marvell/dreamplug/
Dkwbimage.cfg44 # bit7-4: TRCD
64 # bit7-6: 10, Cs1size=1Gb
87 # bit7: 0, TestMode=0 normal
109 # bit7 : 0
/external/vixl/src/
Dutils-vixl.h643 uint32_t bit7 = ((bits >> 31) & 0x1) << 7; in FP32ToImm8() local
648 return static_cast<uint32_t>(bit7 | bit6 | bit5_to_0); in FP32ToImm8()
655 uint64_t bit7 = ((bits >> 63) & 0x1) << 7; in FP64ToImm8() local
661 return static_cast<uint32_t>(bit7 | bit6 | bit5_to_0); in FP64ToImm8()
668 uint32_t bit7 = (bits >> 7) & 0x1; in Imm8ToFP32() local
671 uint32_t result = (bit7 << 31) | ((32 - bit6) << 25) | (bit5_to_0 << 19); in Imm8ToFP32()
681 uint64_t bit7 = (bits >> 7) & 0x1; in Imm8ToFP64() local
684 uint64_t result = (bit7 << 63) | ((256 - bit6) << 54) | (bit5_to_0 << 48); in Imm8ToFP64()
/external/v8/src/arm64/
Dinstructions-arm64.h186 uint32_t bit7 = (bits >> 7) & 0x1; in Imm8ToFP32() local
189 uint32_t result = (bit7 << 31) | ((32 - bit6) << 25) | (bit5_to_0 << 19); in Imm8ToFP32()
200 uint64_t bit7 = (bits >> 7) & 0x1; in Imm8ToFP64() local
203 uint64_t result = (bit7 << 63) | ((256 - bit6) << 54) | (bit5_to_0 << 48); in Imm8ToFP64()

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